Changeset 159 for trunk/MultiChannelUSB/adc_lvds.v
- Timestamp:
- Jan 11, 2012, 4:32:57 PM (13 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/adc_lvds.v
r98 r159 1 2 (* ALTERA_ATTRIBUTE = {"{-to int_data_p} DDIO_INPUT_REGISTER=HIGH; {-to int_data_n} DDIO_INPUT_REGISTER=LOW"} *) 3 1 4 module adc_lvds 2 5 #( … … 5 8 ) 6 9 ( 10 input wire clock, 11 7 12 input wire lvds_dco, 8 13 input wire lvds_fco, 9 14 input wire [size-1:0] lvds_d, 10 15 11 output wire [size*width-1:0] adc_data 16 input wire [1:0] trig, 17 18 output wire adc_frame, 19 output wire [size*width-1+2:0] adc_data 20 12 21 ); 22 localparam width2 = width + 2; 23 13 24 14 wire [size-1:0] int_data_h, int_data_l; 15 reg [width-1:0] int_data_next [size-1:0]; 16 // reg [2*width:0] int_data_next [size-1:0]; 17 reg [width-1:0] int_data_reg [size-1:0]; 18 // reg [2*width:0] int_data_reg [size-1:0]; 25 reg state, int_rdreq, adc_frame_reg; 26 wire int_wrfull, int_rdempty; 19 27 20 reg [width-1:0] int_adc_data [size-1:0];28 reg [size-1:0] int_data_p, int_data_n; 21 29 22 integer i; 30 reg [2:0] int_edge_reg; 31 32 reg [size*width-1:0] int_fifo_reg; 33 wire [size*width-1:0] int_fifo_wire; 34 35 reg [size*width2-1:0] int_data_reg; 36 wire [size*width2-1:0] int_data_wire; 37 38 wire [size*width-1+2:0] int_q_wire; 39 reg [size*width-1+2:0] adc_data_reg; 40 41 42 23 43 genvar j; 24 44 25 altddio_in #( 45 generate 46 for (j = 0; j < size; j = j + 1) 47 begin : INT_DATA 48 // MSB first 49 // assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_p[j], int_data_n[j]}; 50 // LSB first 51 // assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]}; 52 53 assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_reg[j*width2+width2-3:j*width2], int_data_p[j], int_data_n[j]}; 54 assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-1:j*width2+2]; 55 // assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]}; 56 // assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-3:j*width2]; 57 end 58 endgenerate 59 60 61 dcfifo #( 26 62 .intended_device_family("Cyclone III"), 27 .invert_input_clocks("ON"), 28 // .invert_input_clocks("OFF"), 29 .lpm_type("altddio_in"), 30 .width(size)) altddio_in_unit ( 31 .datain(lvds_d), 32 .inclock(lvds_dco), 33 .aclr(1'b0), 34 .dataout_h(int_data_h), 35 .dataout_l(int_data_l), 36 .aset(1'b0), 37 .inclocken(1'b1), 38 .sclr(1'b0), 39 .sset(1'b0)); 63 .lpm_numwords(16), 64 .lpm_showahead("ON"), 65 .lpm_type("dcfifo"), 66 .lpm_width(size*width+2), 67 .lpm_widthu(4), 68 .rdsync_delaypipe(4), 69 .wrsync_delaypipe(4), 70 .overflow_checking("ON"), 71 .underflow_checking("ON"), 72 .use_eab("ON")) fifo_unit ( 73 // .data(int_data_wire), 74 .data({trig, int_fifo_reg}), 75 .rdclk(clock), 76 .rdreq((~int_rdempty) & int_rdreq), 77 .wrclk(lvds_fco), 78 .wrreq(~int_wrfull), 79 .q(int_q_wire), 80 .rdempty(int_rdempty), 81 .wrfull(int_wrfull), 82 .aclr(), 83 .rdfull(), 84 .rdusedw(), 85 .wrempty(), 86 .wrusedw()); 87 88 always @ (posedge clock) 89 begin 90 case (state) 91 1'b0: 92 begin 93 int_rdreq <= 1'b1; 94 adc_frame_reg <= 1'b0; 95 state <= 1'b1; 96 end 97 98 1'b1: 99 begin 100 if (~int_rdempty) 101 begin 102 int_rdreq <= 1'b0; 103 adc_frame_reg <= 1'b1; 104 adc_data_reg <= int_q_wire; 105 state <= 1'b0; 106 end 107 end 108 endcase 109 end 110 111 always @ (negedge lvds_dco) 112 begin 113 int_data_n <= lvds_d; 114 end 40 115 41 116 always @ (posedge lvds_dco) 42 117 begin 43 for (i = 0; i < size; i = i + 1) 118 int_data_p <= lvds_d; 119 int_data_reg <= int_data_wire; 120 int_edge_reg <= {(~int_edge_reg[1]), int_edge_reg[0], lvds_fco}; 121 if (int_edge_reg[1] & int_edge_reg[2]) 44 122 begin 45 int_ data_reg[i] <= int_data_next[i];123 int_fifo_reg <= int_fifo_wire; 46 124 end 47 125 end 48 126 49 always @ (posedge lvds_fco) 50 begin 51 for (i = 0; i < size; i = i + 1) 52 begin 53 int_adc_data[i] <= int_data_next[i]; 54 // int_data_next[i] = {int_data_reg[i][2*width-2:0], int_data_l[i], int_data_h[i]}; 55 end 56 end 57 58 always @* 59 begin 60 for (i = 0; i < size; i = i + 1) 61 begin 62 int_data_next[i] = {int_data_reg[i][width-3:0], int_data_l[i], int_data_h[i]}; 63 // int_data_next[i] = {int_data_reg[i][2*width-2:0], int_data_l[i], int_data_h[i]}; 64 end 65 end 66 67 generate 68 for (j = 0; j < size; j = j + 1) 69 begin : ADC_LVDS_OUTPUT 70 assign adc_data[j*width+width-1:j*width] = int_adc_data[j]; 71 end 72 endgenerate 127 assign adc_frame = adc_frame_reg; 128 assign adc_data = adc_data_reg; 73 129 74 130 endmodule
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