Changeset 144 for sandbox/MultiChannelUSB/deconv.v
- Timestamp:
- May 9, 2011, 5:50:52 PM (14 years ago)
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- 1 edited
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sandbox/MultiChannelUSB/deconv.v (modified) (8 diffs)
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sandbox/MultiChannelUSB/deconv.v
r134 r144 1 1 module deconv 2 2 #( 3 parameter size = 1, // number of channels4 3 parameter shift = 24, // right shift of the result 5 4 parameter width = 27, // bit width of the input data … … 8 7 ( 9 8 input wire clock, frame, reset, 10 input wire [4* size*6-1:0] del_data,11 input wire [4* size*6-1:0] amp_data,12 input wire [4* size*16-1:0] tau_data,13 input wire [4* size*width-1:0] inp_data,14 output wire [4* size*widthr-1:0] out_data9 input wire [4*6-1:0] del_data, 10 input wire [4*6-1:0] amp_data, 11 input wire [4*16-1:0] tau_data, 12 input wire [4*width-1:0] inp_data, 13 output wire [4*widthr-1:0] out_data 15 14 ); 16 15 … … 19 18 localparam width3 = width + 16 + 3; 20 19 21 reg 22 reg 23 reg [1:0] 24 reg [2:0] 25 reg [7:0] 26 27 reg [5:0] 28 wire [5:0] 29 wire [7:0] 30 31 reg [ size*widthr-1:0] out_data_reg [4:0], out_data_next [4:0];32 wire [ size*widthr-1:0] out_data_wire;33 34 wire [ size*width3-1:0] add_data_wire;35 36 wire [ size*width3-1:0] mul_data_wire [1:0];37 38 reg [ size*width2-1:0] acc_data_reg [4:0], acc_data_next [4:0];39 wire [ size*width2-1:0] acc_data_wire;40 41 wire [ size*width1-1:0] sub_data_wire;42 43 reg [ size*width-1:0]inp_data_reg [3:0], inp_data_next [3:0];44 wire [ size*width-1:0]inp_data_wire [4:0];45 46 reg [ size*6-1:0]amp_data_reg, amp_data_next;47 wire [ size*6-1:0]amp_data_wire [3:0];48 49 reg [ size*16-1:0]tau_data_reg, tau_data_next;50 wire [ size*16-1:0]tau_data_wire [3:0];20 reg int_wren_reg, int_wren_next; 21 reg int_flag_reg, int_flag_next; 22 reg [1:0] int_chan_reg, int_chan_next; 23 reg [2:0] int_case_reg, int_case_next; 24 reg [7:0] int_addr_reg, int_addr_next; 25 26 reg [5:0] del_addr_reg, del_addr_next; 27 wire [5:0] del_addr_wire; 28 wire [7:0] int_addr_wire; 29 30 reg [widthr-1:0] out_data_reg [4:0], out_data_next [4:0]; 31 wire [widthr-1:0] out_data_wire; 32 33 wire [width3-1:0] add_data_wire; 34 35 wire [width3-1:0] mul_data_wire [1:0]; 36 37 reg [width2-1:0] acc_data_reg [4:0], acc_data_next [4:0]; 38 wire [width2-1:0] acc_data_wire; 39 40 wire [width1-1:0] sub_data_wire; 41 42 reg [width-1:0] inp_data_reg [3:0], inp_data_next [3:0]; 43 wire [width-1:0] inp_data_wire [4:0]; 44 45 reg [5:0] amp_data_reg, amp_data_next; 46 wire [5:0] amp_data_wire [3:0]; 47 48 reg [15:0] tau_data_reg, tau_data_next; 49 wire [15:0] tau_data_wire [3:0]; 51 50 52 51 integer i; … … 54 53 55 54 generate 56 for (j = 0; j < size; j = j + 1) 57 begin : INT_DATA 58 assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(4*j+0)*width+width-1:(4*j+0)*width]; 59 assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(4*j+1)*width+width-1:(4*j+1)*width]; 60 assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(4*j+2)*width+width-1:(4*j+2)*width]; 61 assign inp_data_wire[3][j*width+width-1:j*width] = inp_data[(4*j+3)*width+width-1:(4*j+3)*width]; 62 assign amp_data_wire[0][j*6+6-1:j*6] = amp_data[(4*j+0)*6+6-1:(4*j+0)*6]; 63 assign amp_data_wire[1][j*6+6-1:j*6] = amp_data[(4*j+1)*6+6-1:(4*j+1)*6]; 64 assign amp_data_wire[2][j*6+6-1:j*6] = amp_data[(4*j+2)*6+6-1:(4*j+2)*6]; 65 assign amp_data_wire[3][j*6+6-1:j*6] = amp_data[(4*j+3)*6+6-1:(4*j+3)*6]; 66 assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(4*j+0)*16+16-1:(4*j+0)*16]; 67 assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(4*j+1)*16+16-1:(4*j+1)*16]; 68 assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(4*j+2)*16+16-1:(4*j+2)*16]; 69 assign tau_data_wire[3][j*16+16-1:j*16] = tau_data[(4*j+3)*16+16-1:(4*j+3)*16]; 70 71 lpm_mux #( 72 .lpm_size(4), 73 .lpm_type("LPM_MUX"), 74 .lpm_width(8), 75 .lpm_widths(2)) mux_unit_1 ( 76 .sel(int_chan_next), 77 .data({ 78 2'd3, del_data[(4*j+3)*6+6-1:(4*j+3)*6], 79 2'd2, del_data[(4*j+2)*6+6-1:(4*j+2)*6], 80 2'd1, del_data[(4*j+1)*6+6-1:(4*j+1)*6], 81 2'd0, del_data[(4*j+0)*6+6-1:(4*j+0)*6]}), 82 .result(int_addr_wire)); 83 84 lpm_add_sub #( 85 .lpm_direction("SUB"), 86 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), 87 .lpm_representation("UNSIGNED"), 88 .lpm_type("LPM_ADD_SUB"), 89 .lpm_width(6)) add_unit_1 ( 90 .dataa(del_addr_reg), 91 .datab(int_addr_wire[5:0]), 92 .result(del_addr_wire)); 93 94 lpm_add_sub #( 95 .lpm_direction("SUB"), 96 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), 97 .lpm_representation("SIGNED"), 98 .lpm_type("LPM_ADD_SUB"), 99 .lpm_width(width1)) sub_unit_1 ( 100 .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}), 101 .datab({{(width1-width){1'b0}}, inp_data_wire[4][j*width+width-1:j*width]}), 102 .result(sub_data_wire[j*width1+width1-1:j*width1])); 103 104 lpm_add_sub #( 105 .lpm_direction("ADD"), 106 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), 107 .lpm_representation("SIGNED"), 108 .lpm_type("LPM_ADD_SUB"), 109 .lpm_width(width2)) acc_unit_1 ( 110 .dataa({{(width2-width1+1){sub_data_wire[j*width1+width1-1]}}, sub_data_wire[j*width1+width1-2:j*width1]}), 111 .datab(acc_data_reg[0][j*width2+width2-1:j*width2]), 112 .result(acc_data_wire[j*width2+width2-1:j*width2])); 113 114 lpm_mult #( 115 .lpm_hint("MAXIMIZE_SPEED=9"), 116 .lpm_representation("SIGNED"), 117 .lpm_type("LPM_MULT"), 118 .lpm_pipeline(3), 119 .lpm_widtha(width1), 120 .lpm_widthb(17), 121 .lpm_widthp(width3)) mult_unit_1 ( 122 .clock(clock), 123 .clken(int_wren_reg), 124 .dataa(sub_data_wire[j*width1+width1-1:j*width1]), 125 .datab({1'b0, tau_data_reg[j*16+16-1:j*16]}), 126 .result(mul_data_wire[0][j*width3+width3-1:j*width3])); 127 128 lpm_mult #( 129 .lpm_hint("MAXIMIZE_SPEED=9"), 130 .lpm_representation("UNSIGNED"), 131 .lpm_type("LPM_MULT"), 132 .lpm_pipeline(3), 133 .lpm_widtha(width2), 134 .lpm_widthb(6), 135 .lpm_widthp(width3)) mult_unit_2 ( 136 .clock(clock), 137 .clken(int_wren_reg), 138 .dataa(acc_data_reg[0][j*width2+width2-1:j*width2]), 139 .datab(amp_data_reg[j*6+6-1:j*6]), 140 .result(mul_data_wire[1][j*width3+width3-1:j*width3])); 141 142 lpm_add_sub #( 143 .lpm_direction("ADD"), 144 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), 145 .lpm_representation("SIGNED"), 146 .lpm_type("LPM_ADD_SUB"), 147 .lpm_width(width3)) add_unit_2 ( 148 .dataa(mul_data_wire[0][j*width3+width3-1:j*width3]), 149 .datab(mul_data_wire[1][j*width3+width3-1:j*width3]), 150 .result(add_data_wire[j*width3+width3-1:j*width3])); 151 152 153 lpm_add_sub #( 154 .lpm_direction("ADD"), 155 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), 156 .lpm_representation("UNSIGNED"), 157 .lpm_type("LPM_ADD_SUB"), 158 .lpm_width(widthr)) add_unit_3 ( 159 .dataa(add_data_wire[j*width3+shift+widthr-1:j*width3+shift]), 160 .datab({{(widthr-1){1'b0}}, add_data_wire[j*width3+shift-1]}), 161 .result(out_data_wire[j*widthr+widthr-1:j*widthr])); 162 55 for (j = 0; j < 4; j = j + 1) 56 begin : INT_DATA 57 assign inp_data_wire[j] = inp_data[j*width+width-1:j*width]; 58 assign amp_data_wire[j] = amp_data[j*6+6-1:j*6]; 59 assign tau_data_wire[j] = tau_data[j*16+16-1:j*16]; 163 60 end 164 61 endgenerate 165 62 63 lpm_mux #( 64 .lpm_size(4), 65 .lpm_type("LPM_MUX"), 66 .lpm_width(8), 67 .lpm_widths(2)) mux_unit_1 ( 68 .sel(int_chan_next), 69 .data({ 70 2'd3, del_data[3*6+6-1:3*6], 71 2'd2, del_data[2*6+6-1:2*6], 72 2'd1, del_data[1*6+6-1:1*6], 73 2'd0, del_data[0*6+6-1:0*6]}), 74 .result(int_addr_wire)); 75 76 assign del_addr_wire = del_addr_reg - int_addr_wire[5:0]; 77 78 assign sub_data_wire = 79 {{(width1-width){1'b0}}, inp_data_reg[0]} 80 - {{(width1-width){1'b0}}, inp_data_wire[4]}; 81 82 assign acc_data_wire = 83 {{(width2-width1+1){sub_data_wire[width1-1]}}, sub_data_wire[width1-2:0]} 84 + acc_data_reg[0]; 85 86 lpm_mult #( 87 .lpm_hint("MAXIMIZE_SPEED=9"), 88 .lpm_representation("SIGNED"), 89 .lpm_type("LPM_MULT"), 90 .lpm_pipeline(3), 91 .lpm_widtha(width1), 92 .lpm_widthb(17), 93 .lpm_widthp(width3)) mult_unit_1 ( 94 .clock(clock), 95 .clken(int_wren_reg), 96 .dataa(sub_data_wire), 97 .datab({1'b0, tau_data_reg}), 98 .result(mul_data_wire[0])); 99 100 lpm_mult #( 101 .lpm_hint("MAXIMIZE_SPEED=9"), 102 .lpm_representation("UNSIGNED"), 103 .lpm_type("LPM_MULT"), 104 .lpm_pipeline(3), 105 .lpm_widtha(width2), 106 .lpm_widthb(6), 107 .lpm_widthp(width3)) mult_unit_2 ( 108 .clock(clock), 109 .clken(int_wren_reg), 110 .dataa(acc_data_reg[0]), 111 .datab(amp_data_reg), 112 .result(mul_data_wire[1])); 113 114 assign add_data_wire = 115 mul_data_wire[0] 116 + mul_data_wire[1]; 117 118 assign out_data_wire = 119 add_data_wire[shift+widthr-1:shift] 120 + {{(widthr-1){add_data_wire[width3-1]}}, add_data_wire[shift-1]}; 166 121 167 122 altsyncram #( … … 182 137 .widthad_a(8), 183 138 .widthad_b(8), 184 .width_a( size*width),185 .width_b( size*width),139 .width_a(width), 140 .width_b(width), 186 141 .width_byteena_a(1)) ram_unit_1 ( 187 142 .wren_a(int_wren_reg), … … 202 157 .clocken2(1'b1), 203 158 .clocken3(1'b1), 204 .data_b({( size*width){1'b1}}),159 .data_b({(width){1'b1}}), 205 160 .eccstatus(), 206 161 .q_a(), … … 223 178 for(i = 0; i <= 3; i = i + 1) 224 179 begin 225 inp_data_reg[i] <= {( size*width){1'b0}};180 inp_data_reg[i] <= {(width){1'b0}}; 226 181 end 227 182 for(i = 0; i <= 4; i = i + 1) 228 183 begin 229 acc_data_reg[i] <= {( size*width2){1'b0}};230 out_data_reg[i] <= {( size*widthr){1'b0}};184 acc_data_reg[i] <= {(width2){1'b0}}; 185 out_data_reg[i] <= {(widthr){1'b0}}; 231 186 end 232 187 end … … 284 239 for(i = 0; i <= 3; i = i + 1) 285 240 begin 286 inp_data_next[i] = {( size*width){1'b0}};241 inp_data_next[i] = {(width){1'b0}}; 287 242 end 288 243 for(i = 0; i <= 4; i = i + 1) 289 244 begin 290 acc_data_next[i] = {( size*width2){1'b0}};291 out_data_next[i] = {( size*widthr){1'b0}};245 acc_data_next[i] = {(width2){1'b0}}; 246 out_data_next[i] = {(widthr){1'b0}}; 292 247 end 293 248
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