Changeset 144 for sandbox/MultiChannelUSB/clip.v
- Timestamp:
- May 9, 2011, 5:50:52 PM (14 years ago)
- File:
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- 1 edited
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sandbox/MultiChannelUSB/clip.v (modified) (7 diffs)
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sandbox/MultiChannelUSB/clip.v
r139 r144 1 1 module clip 2 2 #( 3 parameter size = 1, // number of channels4 3 parameter shift = 24, // right shift of the result 5 4 parameter width = 27, // bit width of the input data … … 7 6 ) 8 7 ( 9 input wire 10 input wire [4* size*6-1:0] del_data,11 input wire [4* size*6-1:0] amp_data,12 input wire [4* size*16-1:0] tau_data,13 input wire [4* size*width-1:0] inp_data,14 output wire [4* size*widthr-1:0] out_data8 input wire clock, frame, reset, 9 input wire [4*6-1:0] del_data, 10 input wire [4*6-1:0] amp_data, 11 input wire [4*16-1:0] tau_data, 12 input wire [4*width-1:0] inp_data, 13 output wire [4*widthr-1:0] out_data 15 14 ); 16 15 … … 19 18 localparam width3 = width1 + 2; 20 19 21 reg 22 reg 23 reg [1:0] 24 reg [2:0] 25 reg [7:0] 26 27 reg [5:0] 28 wire [5:0] 29 wire [7:0] 30 31 reg [ size*widthr-1:0] out_data_reg [4:0], out_data_next [4:0];32 wire [ size*widthr-1:0] out_data_wire;33 34 wire [ size*width3-1:0] add_data_wire;35 36 wire [ size*width1-1:0] mul_data_wire1;37 wire [ size*width2-1:0] mul_data_wire2;38 39 reg [ size*width-1:0]inp_data_reg [3:0], inp_data_next [3:0];40 wire [ size*width-1:0]inp_data_wire [4:0];41 42 reg [ size*6-1:0]amp_data_reg, amp_data_next;43 wire [ size*6-1:0]amp_data_wire [3:0];44 45 reg [ size*16-1:0]tau_data_reg, tau_data_next;46 wire [ size*16-1:0]tau_data_wire [3:0];20 reg int_wren_reg, int_wren_next; 21 reg int_flag_reg, int_flag_next; 22 reg [1:0] int_chan_reg, int_chan_next; 23 reg [2:0] int_case_reg, int_case_next; 24 reg [7:0] int_addr_reg, int_addr_next; 25 26 reg [5:0] del_addr_reg, del_addr_next; 27 wire [5:0] del_addr_wire; 28 wire [7:0] int_addr_wire; 29 30 reg [widthr-1:0] out_data_reg [4:0], out_data_next [4:0]; 31 wire [widthr-1:0] out_data_wire; 32 33 wire [width3-1:0] add_data_wire; 34 35 wire [width1-1:0] mul_data_wire1; 36 wire [width2-1:0] mul_data_wire2; 37 38 reg [width-1:0] inp_data_reg [3:0], inp_data_next [3:0]; 39 wire [width-1:0] inp_data_wire [4:0]; 40 41 reg [5:0] amp_data_reg, amp_data_next; 42 wire [5:0] amp_data_wire [3:0]; 43 44 reg [15:0] tau_data_reg, tau_data_next; 45 wire [15:0] tau_data_wire [3:0]; 47 46 48 47 integer i; 49 genvar j; 48 genvar j; 50 49 51 50 generate 52 for (j = 0; j < size; j = j + 1) 53 begin : INT_DATA 54 assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(4*j+0)*width+width-1:(4*j+0)*width]; 55 assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(4*j+1)*width+width-1:(4*j+1)*width]; 56 assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(4*j+2)*width+width-1:(4*j+2)*width]; 57 assign inp_data_wire[3][j*width+width-1:j*width] = inp_data[(4*j+3)*width+width-1:(4*j+3)*width]; 58 assign amp_data_wire[0][j*6+6-1:j*6] = amp_data[(4*j+0)*6+6-1:(4*j+0)*6]; 59 assign amp_data_wire[1][j*6+6-1:j*6] = amp_data[(4*j+1)*6+6-1:(4*j+1)*6]; 60 assign amp_data_wire[2][j*6+6-1:j*6] = amp_data[(4*j+2)*6+6-1:(4*j+2)*6]; 61 assign amp_data_wire[3][j*6+6-1:j*6] = amp_data[(4*j+3)*6+6-1:(4*j+3)*6]; 62 assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(4*j+0)*16+16-1:(4*j+0)*16]; 63 assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(4*j+1)*16+16-1:(4*j+1)*16]; 64 assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(4*j+2)*16+16-1:(4*j+2)*16]; 65 assign tau_data_wire[3][j*16+16-1:j*16] = tau_data[(4*j+3)*16+16-1:(4*j+3)*16]; 66 67 lpm_mux #( 68 .lpm_size(4), 69 .lpm_type("LPM_MUX"), 70 .lpm_width(8), 71 .lpm_widths(2)) mux_unit_1 ( 72 .sel(int_chan_next), 73 .data({ 74 2'd3, del_data[(4*j+3)*6+6-1:(4*j+3)*6], 75 2'd2, del_data[(4*j+2)*6+6-1:(4*j+2)*6], 76 2'd1, del_data[(4*j+1)*6+6-1:(4*j+1)*6], 77 2'd0, del_data[(4*j+0)*6+6-1:(4*j+0)*6]}), 78 .result(int_addr_wire)); 79 /* 80 lpm_add_sub #( 81 .lpm_direction("SUB"), 82 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), 83 .lpm_representation("UNSIGNED"), 84 .lpm_type("LPM_ADD_SUB"), 85 .lpm_width(6)) add_unit_1 ( 86 .dataa(del_addr_reg), 87 .datab(int_addr_wire[5:0]), 88 .result(del_addr_wire)); 89 */ 90 assign del_addr_wire = del_addr_reg - int_addr_wire[5:0]; 91 92 lpm_mult #( 93 .lpm_hint("MAXIMIZE_SPEED=9"), 94 .lpm_representation("UNSIGNED"), 95 .lpm_type("LPM_MULT"), 96 .lpm_pipeline(3), 97 .lpm_widtha(width), 98 .lpm_widthb(16), 99 .lpm_widthp(width1)) mult_unit_1 ( 100 .clock(clock), 101 .clken(int_wren_reg), 102 .dataa(inp_data_wire[4][j*width+width-1:j*width]), 103 .datab(tau_data_reg[j*16+16-1:j*16]), 104 .result(mul_data_wire1[j*width1+width1-1:j*width1])); 105 106 lpm_mult #( 107 .lpm_hint("MAXIMIZE_SPEED=9"), 108 .lpm_representation("UNSIGNED"), 109 .lpm_type("LPM_MULT"), 110 .lpm_pipeline(3), 111 .lpm_widtha(width), 112 .lpm_widthb(6), 113 .lpm_widthp(width2)) mult_unit_2 ( 114 .clock(clock), 115 .clken(int_wren_reg), 116 .dataa(inp_data_reg[0][j*width+width-1:j*width]), 117 .datab(amp_data_reg[j*6+6-1:j*6]), 118 .result(mul_data_wire2[j*width2+width2-1:j*width2])); 119 /* 120 lpm_add_sub #( 121 .lpm_direction("SUB"), 122 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), 123 .lpm_representation("UNSIGNED"), 124 .lpm_type("LPM_ADD_SUB"), 125 .lpm_width(width3)) add_unit_2 ( 126 .dataa({2'b0, mul_data_wire2[j*width2+width2-1:j*width2], {(width1-width2){1'b0}}}), 127 .datab({2'b0, mul_data_wire1[j*width1+width1-1:j*width1]}), 128 .result(add_data_wire[j*width3+width3-1:j*width3])); 129 */ 130 assign add_data_wire[j*width3+width3-1:j*width3] = 131 {2'b0, mul_data_wire2[j*width2+width2-1:j*width2], {(width1-width2){1'b0}}} 132 - {2'b0, mul_data_wire1[j*width1+width1-1:j*width1]}; 133 /* 134 lpm_add_sub #( 135 .lpm_direction("ADD"), 136 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), 137 .lpm_representation("UNSIGNED"), 138 .lpm_type("LPM_ADD_SUB"), 139 .lpm_width(widthr)) add_unit_3 ( 140 .dataa(add_data_wire[j*width3+shift+widthr-1:j*width3+shift]), 141 .datab({{(widthr-1){add_data_wire[j*width3+width3-1]}}, add_data_wire[j*width3+shift-1]}), 142 .result(out_data_wire[j*widthr+widthr-1:j*widthr])); 143 */ 144 assign out_data_wire[j*widthr+widthr-1:j*widthr] = 145 add_data_wire[j*width3+shift+widthr-1:j*width3+shift] 146 + {{(widthr-1){add_data_wire[j*width3+width3-1]}}, add_data_wire[j*width3+shift-1]}; 147 51 for (j = 0; j < 4; j = j + 1) 52 begin : INT_DATA 53 assign inp_data_wire[j] = inp_data[j*width+width-1:j*width]; 54 assign amp_data_wire[j] = amp_data[j*6+6-1:j*6]; 55 assign tau_data_wire[j] = tau_data[j*16+16-1:j*16]; 148 56 end 149 57 endgenerate 58 59 lpm_mux #( 60 .lpm_size(4), 61 .lpm_type("LPM_MUX"), 62 .lpm_width(8), 63 .lpm_widths(2)) mux_unit_1 ( 64 .sel(int_chan_next), 65 .data({ 66 2'd3, del_data[3*6+6-1:3*6], 67 2'd2, del_data[2*6+6-1:2*6], 68 2'd1, del_data[1*6+6-1:1*6], 69 2'd0, del_data[0*6+6-1:0*6]}), 70 .result(int_addr_wire)); 71 72 assign del_addr_wire = del_addr_reg - int_addr_wire[5:0]; 73 74 lpm_mult #( 75 .lpm_hint("MAXIMIZE_SPEED=9"), 76 .lpm_representation("UNSIGNED"), 77 .lpm_type("LPM_MULT"), 78 .lpm_pipeline(3), 79 .lpm_widtha(width), 80 .lpm_widthb(16), 81 .lpm_widthp(width1)) mult_unit_1 ( 82 .clock(clock), 83 .clken(int_wren_reg), 84 .dataa(inp_data_wire[4]), 85 .datab(tau_data_reg), 86 .result(mul_data_wire1)); 87 88 lpm_mult #( 89 .lpm_hint("MAXIMIZE_SPEED=9"), 90 .lpm_representation("UNSIGNED"), 91 .lpm_type("LPM_MULT"), 92 .lpm_pipeline(3), 93 .lpm_widtha(width), 94 .lpm_widthb(6), 95 .lpm_widthp(width2)) mult_unit_2 ( 96 .clock(clock), 97 .clken(int_wren_reg), 98 .dataa(inp_data_reg[0]), 99 .datab(amp_data_reg), 100 .result(mul_data_wire2)); 101 102 assign add_data_wire = 103 {2'b0, mul_data_wire2, {(width1-width2){1'b0}}} 104 - {2'b0, mul_data_wire1}; 105 106 assign out_data_wire = 107 add_data_wire[shift+widthr-1:shift] 108 + {{(widthr-1){add_data_wire[width3-1]}}, add_data_wire[shift-1]}; 150 109 151 110 … … 167 126 .widthad_a(8), 168 127 .widthad_b(8), 169 .width_a( size*width),170 .width_b( size*width),128 .width_a(width), 129 .width_b(width), 171 130 .width_byteena_a(1)) ram_unit_1 ( 172 131 .wren_a(int_wren_reg), … … 187 146 .clocken2(1'b1), 188 147 .clocken3(1'b1), 189 .data_b({( size*width){1'b1}}),148 .data_b({(width){1'b1}}), 190 149 .eccstatus(), 191 150 .q_a(), … … 208 167 for(i = 0; i <= 3; i = i + 1) 209 168 begin 210 inp_data_reg[i] <= {( size*width){1'b0}};169 inp_data_reg[i] <= {(width){1'b0}}; 211 170 end 212 171 for(i = 0; i <= 4; i = i + 1) 213 172 begin 214 out_data_reg[i] <= {( size*widthr){1'b0}};173 out_data_reg[i] <= {(widthr){1'b0}}; 215 174 end 216 175 end … … 266 225 for(i = 0; i <= 3; i = i + 1) 267 226 begin 268 inp_data_next[i] = {( size*width){1'b0}};227 inp_data_next[i] = {(width){1'b0}}; 269 228 end 270 229 for(i = 0; i <= 4; i = i + 1) 271 230 begin 272 out_data_next[i] = {( size*widthr){1'b0}};231 out_data_next[i] = {(widthr){1'b0}}; 273 232 end 274 233
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