Changeset 141
- Timestamp:
- May 8, 2011, 11:15:11 PM (13 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
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sandbox/MultiChannelUSB/spi_fifo.v
r107 r141 1 1 module spi_fifo 2 2 ( 3 input wireclock, reset,3 input wire clock, reset, 4 4 5 input wirebus_ssel, bus_wren,6 input 5 input wire bus_ssel, bus_wren, 6 input wire [15:0] bus_mosi, 7 7 8 output wire 8 output wire bus_busy, 9 9 10 output wire 11 output wire 12 output wire 10 output wire [1:0] spi_sel, 11 output wire spi_sdo, 12 output wire spi_clk 13 13 ); 14 14 15 wire 16 wire [ 15:0] int_q;15 wire int_rdempty, int_wrfull; 16 wire [31:0] int_q; 17 17 18 18 reg int_bus_busy; 19 19 reg int_rdreq, int_wrreq; 20 reg int_clken, int_sdo, int_sel; 21 reg [15:0] int_bus_mosi; 22 reg [15:0] int_data; 23 reg [2:0] clk_cntr; 24 reg [3:0] bit_cntr; 25 reg [1:0] state; 20 reg int_clken, int_sdo; 21 reg [1:0] int_sel; 22 reg [15:0] int_bus_mosi; 23 reg [31:0] int_data; 24 reg [2:0] clk_cntr; 25 reg [4:0] bit_cntr; 26 reg [1:0] state; 26 27 27 scfifo #( 28 .add_ram_output_register("OFF"), 28 dcfifo_mixed_widths #( 29 29 .intended_device_family("Cyclone III"), 30 30 .lpm_numwords(16), 31 31 .lpm_showahead("ON"), 32 .lpm_type(" scfifo"),32 .lpm_type("dcfifo"), 33 33 .lpm_width(16), 34 34 .lpm_widthu(4), 35 .lpm_width_r(32), 36 .lpm_widthu_r(3), 37 .rdsync_delaypipe(4), 38 .wrsync_delaypipe(4), 35 39 .overflow_checking("ON"), 36 40 .underflow_checking("ON"), 37 .use_eab("OFF")) fifo_tx ( 41 .use_eab("ON")) fifo_tx ( 42 .data(int_bus_mosi), 43 .rdclk(clock), 38 44 .rdreq((~int_rdempty) & (int_rdreq) & (&clk_cntr)), 39 .aclr(1'b0), 40 .clock(clock), 45 .wrclk(clock), 41 46 .wrreq(int_wrreq), 42 .data(int_bus_mosi),43 .empty(int_rdempty),44 47 .q(int_q), 45 .full(int_wrfull), 46 .almost_empty(), 47 .almost_full(), 48 .sclr(), 49 .usedw()); 48 .rdempty(int_rdempty), 49 .wrfull(int_wrfull)); 50 50 51 51 always @ (posedge clock) … … 78 78 begin 79 79 int_sdo <= 1'b0; 80 int_sel <= 1'b1;80 int_sel <= 2'b11; 81 81 int_clken <= 1'b0; 82 82 int_rdreq <= 1'b1; … … 89 89 begin 90 90 int_rdreq <= 1'b0; 91 int_data <= int_q;92 bit_cntr <= 4'd0;91 int_data <= {int_q[15:0], int_q[31:16]}; 92 bit_cntr <= 5'd0; 93 93 state <= 2'd2; 94 94 end … … 99 99 begin // data 100 100 int_clken <= 1'b1; 101 int_sel <= 1'b0;102 int_sdo <= int_data[ 11];103 int_data <= {int_data[10:0], 1'b0};104 bit_cntr <= bit_cntr + 4'd1;105 if (bit_cntr == 4'd11)101 int_sel <= int_data[25:24]; 102 int_sdo <= int_data[23]; 103 int_data[23:0] <= {int_data[22:0], 1'b0}; 104 bit_cntr <= bit_cntr + 5'd1; 105 if (bit_cntr == 5'd23) 106 106 begin 107 107 state <= 2'd3;
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