Changeset 140
- Timestamp:
- May 8, 2011, 11:13:17 PM (13 years ago)
- File:
-
- 1 edited
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sandbox/MultiChannelUSB/adc_lvds.v
r107 r140 1 1 module adc_lvds 2 2 #( 3 parameter size = 3, // number of channels4 parameter width = 12// channel resolution3 parameter size = 8, // number of channels 4 parameter width = 24 // channel resolution 5 5 ) 6 6 ( … … 11 11 input wire [size-1:0] lvds_d, 12 12 13 input wire [11:0] test,14 input wire [11:0] trig,15 16 13 output wire adc_frame, 17 output wire [size*width-1 +12:0] adc_data14 output wire [size*width-1:0] adc_data 18 15 19 16 ); 20 17 localparam width2 = width + 1; 18 21 19 reg state, int_rdreq, adc_frame_reg; 22 20 wire int_wrfull, int_rdempty; 23 21 24 reg [size-1:0] int_data_ h, int_data_l;22 reg [size-1:0] int_data_p, int_data_n; 25 23 26 reg [size*width-1:0] int_data_reg; 27 wire [size*width-1:0] int_data_wire; 24 reg [2:0] int_edge_reg; 28 25 29 wire [size*width-1+12:0] int_q_wire; 30 reg [size*width-1+12:0] adc_data_reg; 26 reg [size*width-1:0] int_fifo_reg; 27 wire [size*width-1:0] int_fifo_wire; 28 29 reg [size*width2-1:0] int_data_reg; 30 wire [size*width2-1:0] int_data_wire; 31 32 wire [size*width-1:0] int_q_wire; 33 reg [size*width-1:0] adc_data_reg; 31 34 35 32 36 33 37 genvar j; 34 38 35 39 generate 36 for (j = 0; j < size -1; j = j + 1)40 for (j = 0; j < size; j = j + 1) 37 41 begin : INT_DATA 38 assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_h[j], int_data_l[j]}; 39 // assign int_data_wire[j*width+width-1:j*width] = test; 42 // MSB first 43 // assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_p[j], int_data_n[j]}; 44 // LSB first 45 // assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]}; 46 assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]}; 47 assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-2:j*width2]; 40 48 end 41 49 endgenerate 42 assign int_data_wire[(size-1)*width+width-1:(size-1)*width] = test;43 50 44 51 dcfifo #( … … 47 54 .lpm_showahead("ON"), 48 55 .lpm_type("dcfifo"), 49 .lpm_width(size*width +12),56 .lpm_width(size*width), 50 57 .lpm_widthu(4), 51 58 .rdsync_delaypipe(4), … … 54 61 .underflow_checking("ON"), 55 62 .use_eab("ON")) fifo_unit ( 56 .data({trig, int_data_wire}), 63 // .data(int_data_wire), 64 .data(int_fifo_reg), 57 65 .rdclk(clock), 58 66 .rdreq((~int_rdempty) & int_rdreq), … … 93 101 always @ (negedge lvds_dco) 94 102 begin 95 int_data_ l<= lvds_d;103 int_data_n <= lvds_d; 96 104 end 97 105 98 106 always @ (posedge lvds_dco) 99 107 begin 100 int_data_ h<= lvds_d;108 int_data_p <= lvds_d; 101 109 int_data_reg <= int_data_wire; 110 int_edge_reg <= {int_edge_reg[1:0], lvds_fco}; 111 if (int_edge_reg[1] & (~int_edge_reg[2])) 112 begin 113 int_fifo_reg <= int_fifo_wire; 114 end 102 115 end 103 116
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