Changeset 130 for sandbox/MultiChannelUSB/deconv.v
- Timestamp:
- Feb 25, 2011, 5:49:51 PM (14 years ago)
- File:
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- 1 edited
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sandbox/MultiChannelUSB/deconv.v (modified) (24 diffs)
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sandbox/MultiChannelUSB/deconv.v
r129 r130 8 8 ( 9 9 input wire clock, frame, reset, 10 input wire [ 3*size*6-1:0] del_data,11 input wire [ 3*size*6-1:0] amp_data,12 input wire [ 3*size*16-1:0] tau_data,13 input wire [ 3*size*width-1:0] inp_data,14 output wire [ 3*size*widthr-1:0] out_data10 input wire [4*size*6-1:0] del_data, 11 input wire [4*size*6-1:0] amp_data, 12 input wire [4*size*16-1:0] tau_data, 13 input wire [4*size*width-1:0] inp_data, 14 output wire [4*size*widthr-1:0] out_data 15 15 ); 16 16 … … 20 20 21 21 reg int_wren_reg, int_wren_next; 22 reg int_flag_reg, int_flag_next; 22 23 reg [1:0] int_chan_reg, int_chan_next; 23 24 reg [2:0] int_case_reg, int_case_next; … … 28 29 wire [7:0] int_addr_wire; 29 30 30 reg [size*widthr-1:0] out_data_reg [ 2:0], out_data_next [2:0];31 reg [size*widthr-1:0] out_data_reg [4:0], out_data_next [4:0]; 31 32 wire [size*widthr-1:0] out_data_wire; 32 33 … … 35 36 wire [size*width3-1:0] mul_data_wire [1:0]; 36 37 37 reg [size*width2-1:0] acc_data_reg [ 3:0], acc_data_next [3:0];38 reg [size*width2-1:0] acc_data_reg [4:0], acc_data_next [4:0]; 38 39 wire [size*width2-1:0] acc_data_wire; 39 40 40 41 wire [size*width1-1:0] sub_data_wire; 41 42 42 reg [size*width-1:0] inp_data_reg [ 2:0], inp_data_next [2:0];43 wire [size*width-1:0] inp_data_wire [ 3:0];43 reg [size*width-1:0] inp_data_reg [3:0], inp_data_next [3:0]; 44 wire [size*width-1:0] inp_data_wire [4:0]; 44 45 45 46 reg [size*6-1:0] amp_data_reg, amp_data_next; 46 wire [size*6-1:0] amp_data_wire [ 2:0];47 wire [size*6-1:0] amp_data_wire [3:0]; 47 48 48 49 reg [size*16-1:0] tau_data_reg, tau_data_next; 49 wire [size*16-1:0] tau_data_wire [ 2:0];50 wire [size*16-1:0] tau_data_wire [3:0]; 50 51 51 52 integer i; … … 55 56 for (j = 0; j < size; j = j + 1) 56 57 begin : INT_DATA 57 assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(3*j+0)*width+width-1:(3*j+0)*width]; 58 assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(3*j+1)*width+width-1:(3*j+1)*width]; 59 assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(3*j+2)*width+width-1:(3*j+2)*width]; 60 assign amp_data_wire[0][j*6+6-1:j*6] = amp_data[(3*j+0)*6+6-1:(3*j+0)*6]; 61 assign amp_data_wire[1][j*6+6-1:j*6] = amp_data[(3*j+1)*6+6-1:(3*j+1)*6]; 62 assign amp_data_wire[2][j*6+6-1:j*6] = amp_data[(3*j+2)*6+6-1:(3*j+2)*6]; 63 assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(3*j+0)*16+16-1:(3*j+0)*16]; 64 assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(3*j+1)*16+16-1:(3*j+1)*16]; 65 assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(3*j+2)*16+16-1:(3*j+2)*16]; 58 assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(4*j+0)*width+width-1:(4*j+0)*width]; 59 assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(4*j+1)*width+width-1:(4*j+1)*width]; 60 assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(4*j+2)*width+width-1:(4*j+2)*width]; 61 assign inp_data_wire[3][j*width+width-1:j*width] = inp_data[(4*j+3)*width+width-1:(4*j+3)*width]; 62 assign amp_data_wire[0][j*6+6-1:j*6] = amp_data[(4*j+0)*6+6-1:(4*j+0)*6]; 63 assign amp_data_wire[1][j*6+6-1:j*6] = amp_data[(4*j+1)*6+6-1:(4*j+1)*6]; 64 assign amp_data_wire[2][j*6+6-1:j*6] = amp_data[(4*j+2)*6+6-1:(4*j+2)*6]; 65 assign amp_data_wire[3][j*6+6-1:j*6] = amp_data[(4*j+3)*6+6-1:(4*j+3)*6]; 66 assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(4*j+0)*16+16-1:(4*j+0)*16]; 67 assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(4*j+1)*16+16-1:(4*j+1)*16]; 68 assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(4*j+2)*16+16-1:(4*j+2)*16]; 69 assign tau_data_wire[3][j*16+16-1:j*16] = tau_data[(4*j+3)*16+16-1:(4*j+3)*16]; 66 70 67 71 lpm_mux #( 68 .lpm_size( 3),72 .lpm_size(4), 69 73 .lpm_type("LPM_MUX"), 70 74 .lpm_width(8), … … 72 76 .sel(int_chan_next), 73 77 .data({ 74 2'd2, del_data[(3*j+2)*6+6-1:(3*j+2)*6], 75 2'd1, del_data[(3*j+1)*6+6-1:(3*j+1)*6], 76 2'd0, del_data[(3*j+0)*6+6-1:(3*j+0)*6]}), 78 2'd3, del_data[(4*j+3)*6+6-1:(4*j+3)*6], 79 2'd2, del_data[(4*j+2)*6+6-1:(4*j+2)*6], 80 2'd1, del_data[(4*j+1)*6+6-1:(4*j+1)*6], 81 2'd0, del_data[(4*j+0)*6+6-1:(4*j+0)*6]}), 77 82 .result(int_addr_wire)); 78 83 … … 94 99 .lpm_width(width1)) sub_unit_1 ( 95 100 .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}), 96 .datab({{(width1-width){1'b0}}, inp_data_wire[ 3][j*width+width-1:j*width]}),101 .datab({{(width1-width){1'b0}}, inp_data_wire[4][j*width+width-1:j*width]}), 97 102 .result(sub_data_wire[j*width1+width1-1:j*width1])); 98 103 … … 111 116 .lpm_representation("SIGNED"), 112 117 .lpm_type("LPM_MULT"), 113 .lpm_pipeline( 3),118 .lpm_pipeline(4), 114 119 .lpm_widtha(width1), 115 120 .lpm_widthb(17), … … 125 130 .lpm_representation("UNSIGNED"), 126 131 .lpm_type("LPM_MULT"), 127 .lpm_pipeline( 3),132 .lpm_pipeline(4), 128 133 .lpm_widtha(width2), 129 134 .lpm_widthb(6), … … 185 190 .address_b({int_addr_wire[7:6], del_addr_wire}), 186 191 .data_a(inp_data_reg[0]), 187 .q_b(inp_data_wire[ 3]),192 .q_b(inp_data_wire[4]), 188 193 .aclr0(1'b0), 189 194 .aclr1(1'b0), … … 209 214 begin 210 215 int_wren_reg <= 1'b1; 216 int_flag_reg <= 1'b0; 211 217 int_chan_reg <= 2'd0; 212 218 int_case_reg <= 3'd0; … … 215 221 amp_data_reg <= 6'd0; 216 222 tau_data_reg <= 16'd0; 217 for(i = 0; i <= 2; i = i + 1)223 for(i = 0; i <= 3; i = i + 1) 218 224 begin 219 225 inp_data_reg[i] <= {(size*width){1'b0}}; 226 end 227 for(i = 0; i <= 4; i = i + 1) 228 begin 229 acc_data_reg[i] <= {(size*width2){1'b0}}; 220 230 out_data_reg[i] <= {(size*widthr){1'b0}}; 221 end222 for(i = 0; i <= 3; i = i + 1)223 begin224 acc_data_reg[i] <= {(size*width2){1'b0}};225 231 end 226 232 end … … 228 234 begin 229 235 int_wren_reg <= int_wren_next; 236 int_flag_reg <= int_flag_next; 230 237 int_chan_reg <= int_chan_next; 231 238 int_case_reg <= int_case_next; … … 234 241 amp_data_reg <= amp_data_next; 235 242 tau_data_reg <= tau_data_next; 236 for(i = 0; i <= 2; i = i + 1)243 for(i = 0; i <= 3; i = i + 1) 237 244 begin 238 245 inp_data_reg[i] <= inp_data_next[i]; 246 end 247 for(i = 0; i <= 4; i = i + 1) 248 begin 249 acc_data_reg[i] <= acc_data_next[i]; 239 250 out_data_reg[i] <= out_data_next[i]; 240 end241 for(i = 0; i <= 3; i = i + 1)242 begin243 acc_data_reg[i] <= acc_data_next[i];244 251 end 245 252 end … … 249 256 begin 250 257 int_wren_next = int_wren_reg; 258 int_flag_next = int_flag_reg; 251 259 int_chan_next = int_chan_reg; 252 260 int_case_next = int_case_reg; … … 255 263 amp_data_next = amp_data_reg; 256 264 tau_data_next = tau_data_reg; 257 for(i = 0; i <= 2; i = i + 1)265 for(i = 0; i <= 3; i = i + 1) 258 266 begin 259 267 inp_data_next[i] = inp_data_reg[i]; 260 out_data_next[i] = out_data_reg[i];261 268 end 262 for(i = 0; i <= 3; i = i + 1)269 for(i = 0; i <= 4; i = i + 1) 263 270 begin 264 271 acc_data_next[i] = acc_data_reg[i]; 272 out_data_next[i] = out_data_reg[i]; 265 273 end 266 274 … … 274 282 amp_data_next = 6'd0; 275 283 tau_data_next = 16'd0; 276 for(i = 0; i <= 2; i = i + 1)284 for(i = 0; i <= 3; i = i + 1) 277 285 begin 278 286 inp_data_next[i] = {(size*width){1'b0}}; 279 out_data_next[i] = {(size*widthr){1'b0}};280 287 end 281 for(i = 0; i <= 3; i = i + 1)288 for(i = 0; i <= 4; i = i + 1) 282 289 begin 283 290 acc_data_next[i] = {(size*width2){1'b0}}; 291 out_data_next[i] = {(size*widthr){1'b0}}; 284 292 end 285 293 … … 293 301 begin 294 302 int_wren_next = 1'b0; 303 int_flag_next = 1'b0; 295 304 int_chan_next = 2'd0; 296 305 int_case_next = 3'd2; … … 299 308 2: // frame 300 309 begin 310 int_flag_next = 1'b0; 311 int_wren_next = frame; 301 312 if (frame) 302 313 begin 303 int_wren_next = 1'b1;304 305 314 int_addr_next[7:6] = 2'd0; 306 315 … … 308 317 int_chan_next = 2'd1; 309 318 310 // register input data for 2nd and 3rdsums319 // register input data for 2nd, 3rd and 4th sums 311 320 inp_data_next[1] = inp_data_wire[1]; 312 321 inp_data_next[2] = inp_data_wire[2]; 322 inp_data_next[3] = inp_data_wire[3]; 313 323 314 324 // prepare registers for 1st sum … … 321 331 int_case_next = 3'd3; 322 332 end 323 333 if (int_flag_reg) // register 4th sum 334 begin 335 int_addr_next[5:0] = del_addr_reg; 336 // register 4th sum 337 acc_data_next[4] = acc_data_wire; 338 out_data_next[3] = out_data_wire; 339 end 324 340 end 325 341 3: // 1st sum … … 346 362 begin 347 363 int_addr_next[7:6] = 2'd2; 364 365 // set read addr for 4th pipeline 366 int_chan_next = 2'd3; 348 367 349 368 // prepare registers for 3rd sum … … 364 383 5: // 3rd sum 365 384 begin 366 int_wren_next = 1'b0; 367 385 int_flag_next = 1'b1; 386 387 int_addr_next[7:6] = 2'd3; 388 368 389 // set read addr for 1st pipeline 369 390 int_chan_next = 2'd0; 370 391 392 // prepare registers for 4th sum 393 inp_data_next[0] = inp_data_reg[3]; 394 acc_data_next[0] = acc_data_reg[4]; 395 396 tau_data_next = tau_data_wire[3]; 397 amp_data_next = amp_data_wire[3]; 398 371 399 // register 3rd sum 372 400 acc_data_next[3] = acc_data_wire; 373 401 out_data_next[2] = out_data_wire; 374 402 375 int_addr_next[5:0] = del_addr_reg; 403 // register 4th output 404 out_data_next[4] = out_data_next[3]; 376 405 377 406 int_case_next = 3'd2; … … 384 413 end 385 414 386 assign out_data = {out_data_ reg[2], out_data_reg[1], out_data_reg[0]};415 assign out_data = {out_data_next[4], out_data_reg[2], out_data_reg[1], out_data_reg[0]}; 387 416 388 417 endmodule
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