Changeset 123 for sandbox/MultiChannelUSB/amplitude.v

Timestamp:

Feb 21, 2011, 12:33:56 AM (14 years ago)

Author:

demin

Message:

first more or less working version

File:

• sandbox/MultiChannelUSB/amplitude.v (modified) (5 diffs)

sandbox/MultiChannelUSB/amplitude.v

@@ -1 +1 @@
 module amplitude
+        #(
+                parameter       width   =       12 // bit width of the input data
+        )
         (
-                input   wire                    clock, frame, reset,
-                input   wire    [11:0]  cfg_data,
-                input   wire    [1:0]   uwt_flag,
-                input   wire    [11:0]  uwt_data,
-                output  wire                    amp_good,
-                output  wire    [11:0]  amp_data
+                input   wire                            clock, frame, reset,
+                input   wire    [width-1:0]     cfg_data,
+                input   wire    [width-1:0]     inp_data,
+                output  wire    [width-1:0]     out_data,
+                output  wire                            out_flag
         );
 
-        reg                             state_reg, state_next;
-        reg             [11:0]  minimum_reg, minimum_next;
-        reg                             amp_good_reg, amp_good_next;
-        reg             [11:0]  amp_data_reg, amp_data_next;
-        reg             [11:0]  uwt_data_reg, uwt_data_next;
+        reg                                     int_case_reg, int_case_next;
+        reg                                     out_flag_reg, out_flag_next;
+        reg                                     int_flag_reg, int_flag_next;
+        reg             [width-1:0]     int_mini_reg, int_mini_next;
+        reg             [width-1:0]     out_data_reg, out_data_next;
+        reg             [width-1:0]     inp_data_reg, inp_data_next;
+
+        wire                            int_comp_wire;
+        reg                                     int_comp_reg, int_comp_next;
+
+        assign int_comp_wire = (inp_data_reg < inp_data);
 
         always @(posedge clock)
@@ -19 +27 @@
                 if (reset)
                 begin
-                        state_reg <= 1'b0;
-                        minimum_reg <= 12'd0;
-                        amp_good_reg <= 1'b0;
-                        amp_data_reg <= 12'd0;
-                        uwt_data_reg <= 12'd0;
+                        int_case_reg <= 1'b0;
+                        int_mini_reg <= {(width){1'b0}};
+                        inp_data_reg <= {(width){1'b0}};
+                        out_data_reg <= {(width){1'b0}};
+                        out_flag_reg <= 1'b0;
+                        int_flag_reg <= 1'b0;
+                        int_comp_reg <= 1'b0;
                 end
                 else
                 begin
-                        state_reg <= state_next;
-                        minimum_reg <= minimum_next;
-                        amp_good_reg <= amp_good_next;
-                        amp_data_reg <= amp_data_next;
-                        uwt_data_reg <= uwt_data_next;
+                        int_case_reg <= int_case_next;
+                        int_mini_reg <= int_mini_next;
+                        inp_data_reg <= inp_data_next;
+                        out_data_reg <= out_data_next;
+                        out_flag_reg <= out_flag_next;
+                        int_flag_reg <= int_flag_next;
+                        int_comp_reg <= int_comp_next;
                 end
         end
@@ -37 +49 @@
         always @*
         begin
-                state_next = state_reg;
-                minimum_next = minimum_reg;
-                amp_good_next = amp_good_reg;
-                amp_data_next = amp_data_reg;
-                uwt_data_next = uwt_data_reg;
+                int_case_next = int_case_reg;
+                int_mini_next = int_mini_reg;
+                inp_data_next = inp_data_reg;
+                out_data_next = out_data_reg;
+                out_flag_next = out_flag_reg;
+                int_flag_next = int_flag_reg;
+                int_comp_next = int_comp_reg;
                 
-                case (state_reg)
+                case (int_case_reg)
                         0:
                         begin
                                 if (frame)
                                 begin
-                                        uwt_data_next = uwt_data;
-                                        amp_good_next = 1'b0;
+                                        inp_data_next = inp_data;
+                                        int_comp_next = int_comp_wire;
+                                        out_data_next = {(width){1'b0}};
+                                        out_flag_next = 1'b0;
                                         // minimum
-                                        if (uwt_flag[0])
+                                        if ((~int_comp_reg) & (int_comp_wire))
                                         begin
-                                                minimum_next = uwt_data_reg;
+                                                int_mini_next = inp_data_reg;
+                                                int_flag_next = 1'b1;
                                         end
-                                        else if ((uwt_flag[1]) & (uwt_data > minimum_reg))
+                                        // maximum
+                                        else if ((int_comp_reg) & (~int_comp_wire) & (int_flag_reg))
                                         begin
-                                                amp_data_next = uwt_data - minimum_reg;
-                                                state_next = 1'b1;
+                                                out_data_next = inp_data_reg - int_mini_reg;
+                                                int_flag_next = 1'b0;
+                                                int_case_next = 1'b1;
                                         end
                 end
@@ -65 +84 @@
                         1:
                         begin
-                                amp_good_next = (amp_data_reg >= cfg_data);
-                                state_next = 1'b0;
+                                out_flag_next = (out_data_reg >= cfg_data);
+                                int_case_next = 1'b0;
                         end
 
@@ -72 +91 @@
         end
 
-        assign amp_good = amp_good_reg;
-        assign amp_data = amp_data_reg;
+        assign out_data = out_data_reg;
+        assign out_flag = out_flag_reg;
 
 endmodule