Changeset 114 for sandbox/MultiChannelUSB
- Timestamp:
- Feb 14, 2011, 6:20:15 PM (14 years ago)
- File:
-
- 1 edited
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sandbox/MultiChannelUSB/deconv.v (modified) (20 diffs)
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sandbox/MultiChannelUSB/deconv.v
r113 r114 6 6 ( 7 7 input wire clock, frame, reset, 8 input wire [14:0] del_data, 9 input wire [3*size*32-1:0] mul_data, 8 input wire [3*size*6-1:0] del_data, 9 input wire [3*size*8-1:0] amp_data, 10 input wire [3*size*16-1:0] tau_data, 10 11 input wire [3*size*width-1:0] inp_data, 11 output wire [3*size*widthr-1:0] out_data 12 output wire [3*size*widthr-1:0] out_data, 13 output wire [3*size*width2-1:0] acc_data 12 14 ); 13 15 14 localparam width1 = width + 6 +1;15 localparam width2 = width + 6 + 6;16 localparam widthr = 2*(width + 8);16 localparam width1 = width + 1; 17 localparam width2 = width + 6 + 1; 18 localparam widthr = width + 16 + 3; 17 19 18 20 reg int_wren_reg, int_wren_next; … … 21 23 reg [7:0] int_addr_reg, int_addr_next; 22 24 25 reg [5:0] del_addr_reg, del_addr_next; 26 wire [5:0] del_addr_wire; 23 27 wire [7:0] int_addr_wire; 24 wire [5:0] del_addr_wire; 25 26 reg [size*widthr-1:0] acc_data_reg [6:0], acc_data_next [6:0]; 27 reg [size*widthr-1:0] int_data_reg [17:0], int_data_next [17:0]; 28 29 wire [size*widthr-1:0] int_data_wire [8:0]; 30 31 wire [size*widthr-1:0] mul_data_wire [5:0]; 28 29 reg [size*widthr-1:0] out_data_reg [2:0], out_data_next [2:0]; 30 wire [size*widthr-1:0] out_data_wire; 31 32 reg [size*widthr-1:0] mul_data_reg [7:0], mul_data_next [7:0]; 33 wire [size*widthr-1:0] mul_data_wire [1:0]; 34 35 reg [size*width2-1:0] acc_data_reg [3:0], acc_data_next [3:0]; 36 wire [size*width2-1:0] acc_data_wire; 37 38 reg [size*width1-1:0] sub_data_reg [3:0], sub_data_next [3:0]; 39 wire [size*width1-1:0] sub_data_wire; 40 41 reg [size*width-1:0] inp_data_reg [2:0], inp_data_next [2:0]; 42 wire [size*width-1:0] inp_data_wire [3:0]; 43 44 reg [size*8-1:0] amp_data_reg, amp_data_next; 45 wire [size*8-1:0] amp_data_wire [2:0]; 46 47 reg [size*16-1:0] tau_data_reg, tau_data_next; 48 wire [size*16-1:0] tau_data_wire [2:0]; 32 49 33 50 integer i; … … 37 54 for (j = 0; j < size; j = j + 1) 38 55 begin : INT_DATA 39 assign in t_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+0)*width+width-1:(3*j+0)*width]};40 assign in t_data_wire[1][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+1)*width+width-1:(3*j+1)*width]};41 assign in t_data_wire[2][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+2)*width+width-1:(3*j+2)*width]};42 assign mul_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+0)*16+16-1:(3*j+0)*16]};43 assign mul_data_wire[1][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+1)*16+16-1:(3*j+1)*16]};44 assign mul_data_wire[2][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+2)*16+16-1:(3*j+2)*16]};45 assign mul_data_wire[3][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+3)*16+16-1:(3*j+3)*16]};46 assign mul_data_wire[4][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+4)*16+16-1:(3*j+4)*16]};47 assign mul_data_wire[5][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+5)*16+16-1:(3*j+5)*16]};56 assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(3*j+0)*width+width-1:(3*j+0)*width]; 57 assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(3*j+1)*width+width-1:(3*j+1)*width]; 58 assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(3*j+2)*width+width-1:(3*j+2)*width]; 59 assign amp_data_wire[0][j*8+8-1:j*8] = amp_data[(3*j+0)*8+8-1:(3*j+0)*8]; 60 assign amp_data_wire[1][j*8+8-1:j*8] = amp_data[(3*j+1)*8+8-1:(3*j+1)*8]; 61 assign amp_data_wire[2][j*8+8-1:j*8] = amp_data[(3*j+2)*8+8-1:(3*j+2)*8]; 62 assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(3*j+0)*16+16-1:(3*j+0)*16]; 63 assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(3*j+1)*16+16-1:(3*j+1)*16]; 64 assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(3*j+2)*16+16-1:(3*j+2)*16]; 48 65 66 lpm_mux #( 67 .lpm_size(3), 68 .lpm_type("LPM_MUX"), 69 .lpm_width(8), 70 .lpm_widths(2)) mux_unit_1 ( 71 .sel(int_chan_next), 72 .data({ 73 2'd2, del_data[(3*j+2)*6+6-1:(3*j+2)*6], 74 2'd1, del_data[(3*j+1)*6+6-1:(3*j+1)*6], 75 2'd0, del_data[(3*j+0)*6+6-1:(3*j+0)*6]}), 76 .result(int_addr_wire)); 77 49 78 lpm_add_sub #( 50 .lpm_direction(" ADD"),79 .lpm_direction("SUB"), 51 80 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"), 52 81 .lpm_representation("UNSIGNED"), 53 82 .lpm_type("LPM_ADD_SUB"), 54 83 .lpm_width(6)) add_unit_1 ( 55 .dataa( int_addr_reg[5:0]),84 .dataa(del_addr_reg), 56 85 .datab(int_addr_wire[5:0]), 57 86 .result(del_addr_wire)); … … 62 91 .lpm_representation("SIGNED"), 63 92 .lpm_type("LPM_ADD_SUB"), 64 .lpm_width(width r)) sub_unit_1 (65 .dataa( acc_data_reg[0][j*widthr+widthr-1:j*widthr]),66 .datab( int_data_wire[3][j*widthr+widthr-1:j*widthr]),67 .result( int_data_wire[4][j*widthr+widthr-1:j*widthr]));93 .lpm_width(width1)) sub_unit_1 ( 94 .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}), 95 .datab({{(width1-width){1'b0}}, inp_data_wire[3][j*width+width-1:j*width]}), 96 .result(sub_data_wire[j*width1+width1-1:j*width1])); 68 97 69 98 lpm_add_sub #( … … 72 101 .lpm_representation("SIGNED"), 73 102 .lpm_type("LPM_ADD_SUB"), 74 .lpm_width(widthr)) acc_unit_1 ( 75 .dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]), 76 .datab(acc_data_reg[2][j*widthr+widthr-1:j*widthr]), 77 .result(int_data_wire[5][j*widthr+widthr-1:j*widthr])); 103 .lpm_width(width2)) acc_unit_1 ( 104 .dataa({sub_data_reg[0][j*width1+width1-1], {(width2-width1){1'b0}}, sub_data_reg[0][j*width1+width1-2:j*width1]}), 105 // .dataa({width2{1'b0}}), 106 .datab(acc_data_reg[0][j*width2+width2-1:j*width2]), 107 .result(acc_data_wire[j*width2+width2-1:j*width2])); 78 108 79 109 lpm_mult #( … … 82 112 .lpm_type("LPM_MULT"), 83 113 .lpm_pipeline(3), 84 .lpm_widtha( 18),85 .lpm_widthb(1 8),86 .lpm_widthp( 36)) mult_unit_1 (114 .lpm_widtha(width1), 115 .lpm_widthb(17), 116 .lpm_widthp(widthr)) mult_unit_1 ( 87 117 .clock(clock), 88 118 .clken(int_wren_reg), 89 // .dataa(int_data_wire[4][j*widthr+widthr-1:j*widthr]), 90 .dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]), 91 .datab(acc_data_reg[5][j*widthr+widthr-1:j*widthr]), 92 .result(int_data_wire[6][j*widthr+widthr-1:j*widthr])); 119 .dataa(sub_data_reg[0][j*width1+width1-1:j*width1]), 120 .datab({1'b0, tau_data_reg[j*16+16-1:j*16]}), 121 .result(mul_data_wire[0][j*widthr+widthr-1:j*widthr])); 93 122 94 123 lpm_mult #( 95 124 .lpm_hint("MAXIMIZE_SPEED=9"), 96 .lpm_representation(" SIGNED"),125 .lpm_representation("UNSIGNED"), 97 126 .lpm_type("LPM_MULT"), 98 127 .lpm_pipeline(3), 99 .lpm_widtha(width r),100 .lpm_widthb( widthr),128 .lpm_widtha(width2), 129 .lpm_widthb(8), 101 130 .lpm_widthp(widthr)) mult_unit_2 ( 102 131 .clock(clock), 103 132 .clken(int_wren_reg), 104 // .dataa(int_data_wire[5][j*widthr+widthr-1:j*widthr]), 105 .dataa(acc_data_reg[2][j*widthr+widthr-1:j*widthr]), 106 .datab(acc_data_reg[6][j*widthr+widthr-1:j*widthr]), 107 .result(int_data_wire[7][j*widthr+widthr-1:j*widthr])); 133 .dataa(acc_data_reg[0][j*width2+width2-1:j*width2]), 134 .datab(amp_data_reg[j*8+8-1:j*8]), 135 .result(mul_data_wire[1][j*widthr+widthr-1:j*widthr])); 108 136 109 137 lpm_add_sub #( … … 113 141 .lpm_type("LPM_ADD_SUB"), 114 142 .lpm_width(widthr)) add_unit_2 ( 115 .dataa( acc_data_reg[3][j*widthr+widthr-1:j*widthr]),116 .datab( acc_data_reg[4][j*widthr+widthr-1:j*widthr]),117 .result( int_data_wire[8][j*widthr+widthr-1:j*widthr]));143 .dataa(mul_data_reg[0][j*widthr+widthr-1:j*widthr]), 144 .datab(mul_data_reg[1][j*widthr+widthr-1:j*widthr]), 145 .result(out_data_wire[j*widthr+widthr-1:j*widthr])); 118 146 119 147 end … … 138 166 .widthad_a(8), 139 167 .widthad_b(8), 140 .width_a(size*width r),141 .width_b(size*width r),168 .width_a(size*width), 169 .width_b(size*width), 142 170 .width_byteena_a(1)) ram_unit_1 ( 143 171 .wren_a(int_wren_reg), … … 145 173 .address_a(int_addr_reg), 146 174 .address_b({int_addr_wire[7:6], del_addr_wire}), 147 .data_a( acc_data_reg[0]),148 .q_b(in t_data_wire[3]),175 .data_a(inp_data_reg[0]), 176 .q_b(inp_data_wire[3]), 149 177 .aclr0(1'b0), 150 178 .aclr1(1'b0), … … 158 186 .clocken2(1'b1), 159 187 .clocken3(1'b1), 160 .data_b({ widthr{1'b1}}),188 .data_b({(size*width){1'b1}}), 161 189 .eccstatus(), 162 190 .q_a(), … … 164 192 .rden_b(1'b1), 165 193 .wren_b(1'b0)); 166 167 lpm_mux #(168 .lpm_size(3),169 .lpm_type("LPM_MUX"),170 .lpm_width(8),171 .lpm_widths(2)) mux_unit_1 (172 .sel(int_chan_next),173 .data({174 2'd2, 1'b0, del_data[14:10],175 2'd1, 1'b0, del_data[9:5],176 2'd0, 1'b0, del_data[4:0]}),177 .result(int_addr_wire));178 194 179 195 always @(posedge clock) … … 184 200 int_chan_reg <= 2'd0; 185 201 int_case_reg <= 3'd0; 202 del_addr_reg <= 6'd0; 186 203 int_addr_reg <= 8'd0; 187 for(i = 0; i <= 6; i = i + 1) 188 begin 189 acc_data_reg[i] <= {(size*widthr){1'b0}}; 190 end 191 for(i = 0; i <= 17; i = i + 1) 192 begin 193 int_data_reg[i] <= {(size*widthr){1'b0}}; 204 amp_data_reg <= 8'd0; 205 tau_data_reg <= 16'd0; 206 for(i = 0; i <= 2; i = i + 1) 207 begin 208 inp_data_reg[i] <= {(size*width){1'b0}}; 209 out_data_reg[i] <= {(size*widthr){1'b0}}; 210 end 211 for(i = 0; i <= 3; i = i + 1) 212 begin 213 sub_data_reg[i] <= {(size*width1){1'b0}}; 214 acc_data_reg[i] <= {(size*width2){1'b0}}; 215 end 216 for(i = 0; i <= 7; i = i + 1) 217 begin 218 mul_data_reg[i] <= {(size*widthr){1'b0}}; 194 219 end 195 220 end … … 199 224 int_chan_reg <= int_chan_next; 200 225 int_case_reg <= int_case_next; 226 del_addr_reg <= del_addr_next; 201 227 int_addr_reg <= int_addr_next; 202 for(i = 0; i <= 6; i = i + 1) 203 begin 228 amp_data_reg <= amp_data_next; 229 tau_data_reg <= tau_data_next; 230 for(i = 0; i <= 2; i = i + 1) 231 begin 232 inp_data_reg[i] <= inp_data_next[i]; 233 out_data_reg[i] <= out_data_next[i]; 234 end 235 for(i = 0; i <= 3; i = i + 1) 236 begin 237 sub_data_reg[i] <= sub_data_next[i]; 204 238 acc_data_reg[i] <= acc_data_next[i]; 205 end 206 for(i = 0; i <= 17; i = i + 1)207 begin 208 int_data_reg[i] <= int_data_next[i];239 end 240 for(i = 0; i <= 7; i = i + 1) 241 begin 242 mul_data_reg[i] <= mul_data_next[i]; 209 243 end 210 244 end … … 216 250 int_chan_next = int_chan_reg; 217 251 int_case_next = int_case_reg; 252 del_addr_next = del_addr_reg; 218 253 int_addr_next = int_addr_reg; 219 for(i = 0; i <= 6; i = i + 1) 254 amp_data_next = amp_data_reg; 255 tau_data_next = tau_data_reg; 256 for(i = 0; i <= 2; i = i + 1) 220 257 begin 258 inp_data_next[i] = inp_data_reg[i]; 259 out_data_next[i] = out_data_reg[i]; 260 end 261 for(i = 0; i <= 3; i = i + 1) 262 begin 263 sub_data_next[i] = sub_data_reg[i]; 221 264 acc_data_next[i] = acc_data_reg[i]; 222 end 223 for(i = 0; i <= 17; i = i + 1)265 end 266 for(i = 0; i <= 7; i = i + 1) 224 267 begin 225 int_data_next[i] = int_data_reg[i];268 mul_data_next[i] = mul_data_reg[i]; 226 269 end 227 270 … … 231 274 // write zeros 232 275 int_wren_next = 1'b1; 276 del_addr_next = 6'd0; 233 277 int_addr_next = 8'd0; 234 for(i = 0; i <= 6; i = i + 1) 278 amp_data_next = 8'd0; 279 tau_data_next = 16'd0; 280 for(i = 0; i <= 2; i = i + 1) 235 281 begin 236 acc_data_next[i] = {(size*widthr){1'b0}}; 282 inp_data_next[i] = {(size*width){1'b0}}; 283 out_data_next[i] = {(size*widthr){1'b0}}; 284 end 285 for(i = 0; i <= 3; i = i + 1) 286 begin 287 sub_data_next[i] = {(size*width1){1'b0}}; 288 acc_data_next[i] = {(size*width2){1'b0}}; 289 end 290 for(i = 0; i <= 7; i = i + 1) 291 begin 292 mul_data_next[i] = {(size*widthr){1'b0}}; 237 293 end 238 for(i = 0; i <= 17; i = i + 1) 239 begin 240 int_data_next[i] = {(size*widthr){1'b0}}; 241 end 294 242 295 int_case_next = 3'd1; 243 296 end … … 265 318 266 319 // register input data for 2nd and 3rd sums 267 in t_data_next[0] = int_data_wire[1];268 in t_data_next[1] = int_data_wire[2];320 inp_data_next[1] = inp_data_wire[1]; 321 inp_data_next[2] = inp_data_wire[2]; 269 322 270 323 // prepare registers for 1st sum 271 acc_data_next[0] = int_data_wire[0]; 272 acc_data_next[1] = int_data_reg[2]; 273 acc_data_next[2] = int_data_reg[3]; 274 acc_data_next[3] = int_data_reg[4]; 275 acc_data_next[4] = int_data_reg[5]; 276 acc_data_next[5] = mul_data_wire[0]; 277 acc_data_next[6] = mul_data_wire[1]; 324 inp_data_next[0] = inp_data_wire[0]; 325 326 sub_data_next[0] = sub_data_reg[1]; 327 acc_data_next[0] = acc_data_reg[1]; 328 329 mul_data_next[0] = mul_data_reg[2]; 330 mul_data_next[1] = mul_data_reg[3]; 331 332 tau_data_next = tau_data_wire[0]; 333 amp_data_next = amp_data_wire[0]; 278 334 279 335 int_case_next = 3'd3; … … 289 345 290 346 // prepare registers for 2nd sum 291 acc_data_next[0] = int_data_reg[0]; 292 acc_data_next[1] = int_data_reg[7]; 293 acc_data_next[2] = int_data_reg[8]; 294 acc_data_next[3] = int_data_reg[9]; 295 acc_data_next[4] = int_data_reg[10]; 296 acc_data_next[5] = mul_data_wire[2]; 297 acc_data_next[6] = mul_data_wire[3]; 347 inp_data_next[0] = inp_data_reg[1]; 348 349 sub_data_next[0] = sub_data_reg[2]; 350 acc_data_next[0] = acc_data_reg[2]; 351 352 mul_data_next[0] = mul_data_reg[4]; 353 mul_data_next[1] = mul_data_reg[5]; 354 355 tau_data_next = tau_data_wire[1]; 356 amp_data_next = amp_data_wire[1]; 298 357 299 358 // register 1st sum 300 int_data_next[2] = int_data_wire[4];301 int_data_next[3] = int_data_wire[5];302 int_data_next[4] = int_data_wire[6];303 int_data_next[5] = int_data_wire[7];304 int_data_next[6] = int_data_wire[8];359 sub_data_next[1] = sub_data_wire; 360 acc_data_next[1] = acc_data_wire; 361 mul_data_next[2] = mul_data_wire[0]; 362 mul_data_next[3] = mul_data_wire[1]; 363 out_data_next[0] = out_data_wire; 305 364 306 365 int_case_next = 3'd4; … … 311 370 312 371 // prepare registers for 3rd sum 313 acc_data_next[0] = int_data_reg[1]; 314 acc_data_next[1] = int_data_reg[12]; 315 acc_data_next[2] = int_data_reg[13]; 316 acc_data_next[3] = int_data_reg[14]; 317 acc_data_next[4] = int_data_reg[15]; 318 acc_data_next[5] = mul_data_wire[4]; 319 acc_data_next[6] = mul_data_wire[5]; 372 inp_data_next[0] = inp_data_reg[2]; 373 374 sub_data_next[0] = sub_data_reg[3]; 375 acc_data_next[0] = acc_data_reg[3]; 376 377 mul_data_next[0] = mul_data_reg[6]; 378 mul_data_next[1] = mul_data_reg[7]; 379 380 tau_data_next = tau_data_wire[2]; 381 amp_data_next = amp_data_wire[2]; 320 382 321 383 // register 2nd sum 322 int_data_next[7] = int_data_wire[4];323 int_data_next[8] = int_data_wire[5];324 int_data_next[9] = int_data_wire[6];325 int_data_next[10] = int_data_wire[7];326 int_data_next[11] = int_data_wire[8];384 sub_data_next[2] = sub_data_wire; 385 acc_data_next[2] = acc_data_wire; 386 mul_data_next[4] = mul_data_wire[0]; 387 mul_data_next[5] = mul_data_wire[1]; 388 out_data_next[1] = out_data_wire; 327 389 390 del_addr_next = del_addr_reg + 6'd1; 391 328 392 int_case_next = 3'd5; 329 393 end … … 336 400 337 401 // register 3rd sum 338 int_data_next[12] = int_data_wire[4];339 int_data_next[13] = int_data_wire[5];340 int_data_next[14] = int_data_wire[6];341 int_data_next[15] = int_data_wire[7];342 int_data_next[16] = int_data_wire[8];402 sub_data_next[3] = sub_data_wire; 403 acc_data_next[3] = acc_data_wire; 404 mul_data_next[6] = mul_data_wire[0]; 405 mul_data_next[7] = mul_data_wire[1]; 406 out_data_next[2] = out_data_wire; 343 407 344 int_addr_next[5:0] = int_addr_reg[5:0] + 6'd1;408 int_addr_next[5:0] = del_addr_reg; 345 409 346 410 int_case_next = 3'd2; … … 353 417 end 354 418 355 assign out_data = {int_data_next[16], int_data_next[11], int_data_next[6]}; 419 assign out_data = {out_data_reg[2], out_data_reg[1], out_data_reg[0]}; 420 assign acc_data = {acc_data_reg[3], acc_data_reg[2], acc_data_reg[1]}; 421 // assign acc_data = {17'd0, del_addr_wire, 17'd0, del_addr_wire, 17'd0, del_addr_wire}; 356 422 357 423 endmodule
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