source: sandbox/MultiChannelUSB/deconv.v@ 113

Last change on this file since 113 was 113, checked in by demin, 14 years ago

add deconvolution module
File size: 10.3 KB
Line 
1module deconv
2 #(
3 parameter size = 1, // number of channels
4 parameter width = 16 // bit width of the input data
5 )
6 (
7 input wire clock, frame, reset,
8 input wire [14:0] del_data,
9 input wire [3*size*32-1:0] mul_data,
10 input wire [3*size*width-1:0] inp_data,
11 output wire [3*size*widthr-1:0] out_data
12 );
13
14 localparam width1 = width + 6 + 1;
15 localparam width2 = width + 6 + 6;
16 localparam widthr = 2*(width + 8);
17
18 reg int_wren_reg, int_wren_next;
19 reg [1:0] int_chan_reg, int_chan_next;
20 reg [2:0] int_case_reg, int_case_next;
21 reg [7:0] int_addr_reg, int_addr_next;
22
23 wire [7:0] int_addr_wire;
24 wire [5:0] del_addr_wire;
25
26 reg [size*widthr-1:0] acc_data_reg [6:0], acc_data_next [6:0];
27 reg [size*widthr-1:0] int_data_reg [17:0], int_data_next [17:0];
28
29 wire [size*widthr-1:0] int_data_wire [8:0];
30
31 wire [size*widthr-1:0] mul_data_wire [5:0];
32
33 integer i;
34 genvar j;
35
36 generate
37 for (j = 0; j < size; j = j + 1)
38 begin : INT_DATA
39 assign int_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+0)*width+width-1:(3*j+0)*width]};
40 assign int_data_wire[1][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+1)*width+width-1:(3*j+1)*width]};
41 assign int_data_wire[2][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+2)*width+width-1:(3*j+2)*width]};
42 assign mul_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+0)*16+16-1:(3*j+0)*16]};
43 assign mul_data_wire[1][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+1)*16+16-1:(3*j+1)*16]};
44 assign mul_data_wire[2][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+2)*16+16-1:(3*j+2)*16]};
45 assign mul_data_wire[3][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+3)*16+16-1:(3*j+3)*16]};
46 assign mul_data_wire[4][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+4)*16+16-1:(3*j+4)*16]};
47 assign mul_data_wire[5][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+5)*16+16-1:(3*j+5)*16]};
48
49 lpm_add_sub #(
50 .lpm_direction("ADD"),
51 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
52 .lpm_representation("UNSIGNED"),
53 .lpm_type("LPM_ADD_SUB"),
54 .lpm_width(6)) add_unit_1 (
55 .dataa(int_addr_reg[5:0]),
56 .datab(int_addr_wire[5:0]),
57 .result(del_addr_wire));
58
59 lpm_add_sub #(
60 .lpm_direction("SUB"),
61 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
62 .lpm_representation("SIGNED"),
63 .lpm_type("LPM_ADD_SUB"),
64 .lpm_width(widthr)) sub_unit_1 (
65 .dataa(acc_data_reg[0][j*widthr+widthr-1:j*widthr]),
66 .datab(int_data_wire[3][j*widthr+widthr-1:j*widthr]),
67 .result(int_data_wire[4][j*widthr+widthr-1:j*widthr]));
68
69 lpm_add_sub #(
70 .lpm_direction("ADD"),
71 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
72 .lpm_representation("SIGNED"),
73 .lpm_type("LPM_ADD_SUB"),
74 .lpm_width(widthr)) acc_unit_1 (
75 .dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]),
76 .datab(acc_data_reg[2][j*widthr+widthr-1:j*widthr]),
77 .result(int_data_wire[5][j*widthr+widthr-1:j*widthr]));
78
79 lpm_mult #(
80 .lpm_hint("MAXIMIZE_SPEED=9"),
81 .lpm_representation("SIGNED"),
82 .lpm_type("LPM_MULT"),
83 .lpm_pipeline(3),
84 .lpm_widtha(18),
85 .lpm_widthb(18),
86 .lpm_widthp(36)) mult_unit_1 (
87 .clock(clock),
88 .clken(int_wren_reg),
89// .dataa(int_data_wire[4][j*widthr+widthr-1:j*widthr]),
90 .dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]),
91 .datab(acc_data_reg[5][j*widthr+widthr-1:j*widthr]),
92 .result(int_data_wire[6][j*widthr+widthr-1:j*widthr]));
93
94 lpm_mult #(
95 .lpm_hint("MAXIMIZE_SPEED=9"),
96 .lpm_representation("SIGNED"),
97 .lpm_type("LPM_MULT"),
98 .lpm_pipeline(3),
99 .lpm_widtha(widthr),
100 .lpm_widthb(widthr),
101 .lpm_widthp(widthr)) mult_unit_2 (
102 .clock(clock),
103 .clken(int_wren_reg),
104// .dataa(int_data_wire[5][j*widthr+widthr-1:j*widthr]),
105 .dataa(acc_data_reg[2][j*widthr+widthr-1:j*widthr]),
106 .datab(acc_data_reg[6][j*widthr+widthr-1:j*widthr]),
107 .result(int_data_wire[7][j*widthr+widthr-1:j*widthr]));
108
109 lpm_add_sub #(
110 .lpm_direction("ADD"),
111 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
112 .lpm_representation("SIGNED"),
113 .lpm_type("LPM_ADD_SUB"),
114 .lpm_width(widthr)) add_unit_2 (
115 .dataa(acc_data_reg[3][j*widthr+widthr-1:j*widthr]),
116 .datab(acc_data_reg[4][j*widthr+widthr-1:j*widthr]),
117 .result(int_data_wire[8][j*widthr+widthr-1:j*widthr]));
118
119 end
120 endgenerate
121
122
123 altsyncram #(
124 .address_aclr_b("NONE"),
125 .address_reg_b("CLOCK0"),
126 .clock_enable_input_a("BYPASS"),
127 .clock_enable_input_b("BYPASS"),
128 .clock_enable_output_b("BYPASS"),
129 .intended_device_family("Cyclone III"),
130 .lpm_type("altsyncram"),
131 .numwords_a(256),
132 .numwords_b(256),
133 .operation_mode("DUAL_PORT"),
134 .outdata_aclr_b("NONE"),
135 .outdata_reg_b("CLOCK0"),
136 .power_up_uninitialized("FALSE"),
137 .read_during_write_mode_mixed_ports("DONT_CARE"),
138 .widthad_a(8),
139 .widthad_b(8),
140 .width_a(size*widthr),
141 .width_b(size*widthr),
142 .width_byteena_a(1)) ram_unit_1 (
143 .wren_a(int_wren_reg),
144 .clock0(clock),
145 .address_a(int_addr_reg),
146 .address_b({int_addr_wire[7:6], del_addr_wire}),
147 .data_a(acc_data_reg[0]),
148 .q_b(int_data_wire[3]),
149 .aclr0(1'b0),
150 .aclr1(1'b0),
151 .addressstall_a(1'b0),
152 .addressstall_b(1'b0),
153 .byteena_a(1'b1),
154 .byteena_b(1'b1),
155 .clock1(1'b1),
156 .clocken0(1'b1),
157 .clocken1(1'b1),
158 .clocken2(1'b1),
159 .clocken3(1'b1),
160 .data_b({widthr{1'b1}}),
161 .eccstatus(),
162 .q_a(),
163 .rden_a(1'b1),
164 .rden_b(1'b1),
165 .wren_b(1'b0));
166
167 lpm_mux #(
168 .lpm_size(3),
169 .lpm_type("LPM_MUX"),
170 .lpm_width(8),
171 .lpm_widths(2)) mux_unit_1 (
172 .sel(int_chan_next),
173 .data({
174 2'd2, 1'b0, del_data[14:10],
175 2'd1, 1'b0, del_data[9:5],
176 2'd0, 1'b0, del_data[4:0]}),
177 .result(int_addr_wire));
178
179 always @(posedge clock)
180 begin
181 if (reset)
182 begin
183 int_wren_reg <= 1'b1;
184 int_chan_reg <= 2'd0;
185 int_case_reg <= 3'd0;
186 int_addr_reg <= 8'd0;
187 for(i = 0; i <= 6; i = i + 1)
188 begin
189 acc_data_reg[i] <= {(size*widthr){1'b0}};
190 end
191 for(i = 0; i <= 17; i = i + 1)
192 begin
193 int_data_reg[i] <= {(size*widthr){1'b0}};
194 end
195 end
196 else
197 begin
198 int_wren_reg <= int_wren_next;
199 int_chan_reg <= int_chan_next;
200 int_case_reg <= int_case_next;
201 int_addr_reg <= int_addr_next;
202 for(i = 0; i <= 6; i = i + 1)
203 begin
204 acc_data_reg[i] <= acc_data_next[i];
205 end
206 for(i = 0; i <= 17; i = i + 1)
207 begin
208 int_data_reg[i] <= int_data_next[i];
209 end
210 end
211 end
212
213 always @*
214 begin
215 int_wren_next = int_wren_reg;
216 int_chan_next = int_chan_reg;
217 int_case_next = int_case_reg;
218 int_addr_next = int_addr_reg;
219 for(i = 0; i <= 6; i = i + 1)
220 begin
221 acc_data_next[i] = acc_data_reg[i];
222 end
223 for(i = 0; i <= 17; i = i + 1)
224 begin
225 int_data_next[i] = int_data_reg[i];
226 end
227
228 case (int_case_reg)
229 0:
230 begin
231 // write zeros
232 int_wren_next = 1'b1;
233 int_addr_next = 8'd0;
234 for(i = 0; i <= 6; i = i + 1)
235 begin
236 acc_data_next[i] = {(size*widthr){1'b0}};
237 end
238 for(i = 0; i <= 17; i = i + 1)
239 begin
240 int_data_next[i] = {(size*widthr){1'b0}};
241 end
242 int_case_next = 3'd1;
243 end
244 1:
245 begin
246 // write zeros
247 int_addr_next = int_addr_reg + 8'd1;
248 if (&int_addr_reg)
249 begin
250 int_wren_next = 1'b0;
251 int_chan_next = 2'd0;
252 int_case_next = 3'd2;
253 end
254 end
255 2: // frame
256 begin
257 if (frame)
258 begin
259 int_wren_next = 1'b1;
260
261 int_addr_next[7:6] = 2'd0;
262
263 // set read addr for 2nd pipeline
264 int_chan_next = 2'd1;
265
266 // register input data for 2nd and 3rd sums
267 int_data_next[0] = int_data_wire[1];
268 int_data_next[1] = int_data_wire[2];
269
270 // prepare registers for 1st sum
271 acc_data_next[0] = int_data_wire[0];
272 acc_data_next[1] = int_data_reg[2];
273 acc_data_next[2] = int_data_reg[3];
274 acc_data_next[3] = int_data_reg[4];
275 acc_data_next[4] = int_data_reg[5];
276 acc_data_next[5] = mul_data_wire[0];
277 acc_data_next[6] = mul_data_wire[1];
278
279 int_case_next = 3'd3;
280 end
281
282 end
283 3: // 1st sum
284 begin
285 int_addr_next[7:6] = 2'd1;
286
287 // set read addr for 3rd pipeline
288 int_chan_next = 2'd2;
289
290 // prepare registers for 2nd sum
291 acc_data_next[0] = int_data_reg[0];
292 acc_data_next[1] = int_data_reg[7];
293 acc_data_next[2] = int_data_reg[8];
294 acc_data_next[3] = int_data_reg[9];
295 acc_data_next[4] = int_data_reg[10];
296 acc_data_next[5] = mul_data_wire[2];
297 acc_data_next[6] = mul_data_wire[3];
298
299 // register 1st sum
300 int_data_next[2] = int_data_wire[4];
301 int_data_next[3] = int_data_wire[5];
302 int_data_next[4] = int_data_wire[6];
303 int_data_next[5] = int_data_wire[7];
304 int_data_next[6] = int_data_wire[8];
305
306 int_case_next = 3'd4;
307 end
308 4: // 2nd sum
309 begin
310 int_addr_next[7:6] = 2'd2;
311
312 // prepare registers for 3rd sum
313 acc_data_next[0] = int_data_reg[1];
314 acc_data_next[1] = int_data_reg[12];
315 acc_data_next[2] = int_data_reg[13];
316 acc_data_next[3] = int_data_reg[14];
317 acc_data_next[4] = int_data_reg[15];
318 acc_data_next[5] = mul_data_wire[4];
319 acc_data_next[6] = mul_data_wire[5];
320
321 // register 2nd sum
322 int_data_next[7] = int_data_wire[4];
323 int_data_next[8] = int_data_wire[5];
324 int_data_next[9] = int_data_wire[6];
325 int_data_next[10] = int_data_wire[7];
326 int_data_next[11] = int_data_wire[8];
327
328 int_case_next = 3'd5;
329 end
330 5: // 3rd sum
331 begin
332 int_wren_next = 1'b0;
333
334 // set read addr for 1st pipeline
335 int_chan_next = 2'd0;
336
337 // register 3rd sum
338 int_data_next[12] = int_data_wire[4];
339 int_data_next[13] = int_data_wire[5];
340 int_data_next[14] = int_data_wire[6];
341 int_data_next[15] = int_data_wire[7];
342 int_data_next[16] = int_data_wire[8];
343
344 int_addr_next[5:0] = int_addr_reg[5:0] + 6'd1;
345
346 int_case_next = 3'd2;
347 end
348 default:
349 begin
350 int_case_next = 3'd0;
351 end
352 endcase
353 end
354
355 assign out_data = {int_data_next[16], int_data_next[11], int_data_next[6]};
356
357endmodule
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