Changeset 107 for sandbox/MultiChannelUSB/counter.v

Timestamp:

Jan 17, 2011, 5:56:35 PM (14 years ago)

Author:

demin

Message:

Starting to test signal shaping algorithms

File:

• sandbox/MultiChannelUSB/counter.v (modified) (6 diffs)

sandbox/MultiChannelUSB/counter.v

@@ -1 +1 @@
 module counter
         (
-                input   wire                    clock, frame, reset,
+                input   wire                    clock, frame,
 
-                input   wire    [15:0]  cfg_data,
+                input   wire                    reset, setup, count,
 
                 input   wire                    bus_ssel, bus_wren,
@@ -23 +23 @@
         wire    [63:0]  reg_bits_wire;
         wire    [63:0]  cnt_bits_wire;
+        
+        reg                             int_load_reg;
 
         integer i;
@@ -32 +34 @@
                 .lpm_type("LPM_COUNTER"),
                 .lpm_width(64)) lpm_counter_component (
-                .sload(cfg_data[0]),
+                .sload(int_load_reg | setup),
                 .sclr(reset),
                 .clock(clock),
                 .data(reg_bits_wire),
-//              .cnt_en(frame & cfg_data[1]),
-                .cnt_en((frame) & (|cnt_bits_wire) & (cfg_data[1])),
-                .q(cnt_bits_wire),
-                .aclr(1'b0),
-                .aload(1'b0),
-                .aset(1'b0),
-                .cin(1'b1),
-                .clk_en(1'b1),
-                .cout(),
-                .eq(),
-                .sset(1'b0),
-                .updown(1'b1));
+                .cnt_en((frame) & (count) & (|cnt_bits_wire)),
+                .q(cnt_bits_wire));
 
         generate
@@ -60 +52 @@
                                 .clock(clock),
                                 .data(bus_mosi),
-                                .q(reg_bits_wire[j*16+15:j*16]),
-                                .aclr(),
-                                .aload(),
-                                .aset(),
-                                .sload(),
-                                .sset());
+                                .q(reg_bits_wire[j*16+15:j*16]));
                                 end
         endgenerate
@@ -84 +71 @@
                 .lpm_width(2)) lpm_decode_unit (
                 .data(bus_addr),
-                .eq(int_ssel_wire),
-                .aclr(),
-                .clken(),
-                .clock(),
-                .enable());
+                .eq(int_ssel_wire));
 
         always @(posedge clock)
@@ -96 +79 @@
                         int_miso_reg <= 16'd0;
                         cnt_good_reg <= 1'b0;
+                        int_load_reg <= 1'b0;
                 end
                 else
                 begin
                         int_miso_reg <= int_miso_wire;
-                        cnt_good_reg <= (|cnt_bits_wire) & (cfg_data[1]);
+                        cnt_good_reg <= |cnt_bits_wire;
+                        int_load_reg <= bus_ssel & bus_wren;
                 end
         end