Changeset 107 for sandbox/MultiChannelUSB/Paella.qsf

Timestamp:

Jan 17, 2011, 5:56:35 PM (14 years ago)

Author:

demin

Message:

Starting to test signal shaping algorithms

File:

• sandbox/MultiChannelUSB/Paella.qsf (modified) (3 diffs)

sandbox/MultiChannelUSB/Paella.qsf

@@ -42 +42 @@
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:14  AUGUST 28, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION 9.0
+set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
 set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
@@ -49 +49 @@
 set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
 set_global_assignment -name MISC_FILE Paella.dpf
+set_global_assignment -name MISC_FILE "C:/altera/project_12/Paella.dpf"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name VERILOG_FILE cic_pipeline.v
+set_global_assignment -name VERILOG_FILE cic_filter.v
 set_global_assignment -name VERILOG_FILE Paella.v
-set_global_assignment -name VERILOG_FILE adc_fifo.v
 set_global_assignment -name VERILOG_FILE adc_lvds.v
-set_global_assignment -name VERILOG_FILE adc_para.v
-set_global_assignment -name VERILOG_FILE adc_pll.v
+set_global_assignment -name VERILOG_FILE sys_pll.v
 set_global_assignment -name VERILOG_FILE control.v
+set_global_assignment -name VERILOG_FILE uwt_bior31.v
 set_global_assignment -name VERILOG_FILE analyser.v
+set_global_assignment -name VERILOG_FILE amplitude.v
+set_global_assignment -name VERILOG_FILE delay.v
+set_global_assignment -name VERILOG_FILE coincidence.v
 set_global_assignment -name VERILOG_FILE counter.v
-set_global_assignment -name VERILOG_FILE histogram.v
+set_global_assignment -name VERILOG_FILE histogram32.v
+set_global_assignment -name VERILOG_FILE histogram16.v
 set_global_assignment -name VERILOG_FILE trigger.v
 set_global_assignment -name VERILOG_FILE oscilloscope.v
@@ -63 +70 @@
 set_global_assignment -name VERILOG_FILE usb_fifo.v
 set_global_assignment -name VERILOG_FILE i2c_fifo.v
-set_global_assignment -name VERILOG_FILE uwt_bior31.v
 set_global_assignment -name VERILOG_FILE test.v
-set_global_assignment -name VERILOG_FILE test_pll.v
-set_global_assignment -name VERILOG_FILE sys_pll.v
+set_global_assignment -name MIF_FILE test.mif
 set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
 set_global_assignment -name ENABLE_CLOCK_LATENCY ON