source: trunk/MultiChannelUSB/oscilloscope.v@ 90

Last change on this file since 90 was 90, checked in by demin, 16 years ago

full rewrite
File size: 5.2 KB
RevLine 
[27]1module oscilloscope
2 (
[90]3 input wire clock, frame, reset,
4
5 input wire [16:0] cfg_data,
6
7 input wire trg_flag,
8
9 input wire [47:0] osc_data,
10
11 output wire ram_wren,
12 output wire [19:0] ram_addr,
13 inout wire [17:0] ram_data,
14
15 input wire bus_ssel, bus_wren,
16 input wire [19:0] bus_addr,
17 input wire [15:0] bus_mosi,
18
19 output wire [15:0] bus_miso,
20 output wire bus_busy
[27]21 );
22
23
[90]24 reg [47:0] osc_data_reg, osc_data_next;
[27]25
[90]26 reg [19:0] cfg_cntr_max_reg, cfg_cntr_max_next;
27 reg [19:0] cfg_cntr_mid_reg, cfg_cntr_mid_next;
[51]28
[90]29 reg [2:0] int_case_reg, int_case_next;
30
31 reg int_trig_reg, int_trig_next;
32 reg [19:0] int_trig_addr_reg, int_trig_addr_next;
33 reg [19:0] int_cntr_reg, int_cntr_next;
34
35 reg [15:0] bus_mosi_reg [2:0];
36 reg [15:0] bus_mosi_next [2:0];
37
38 reg [15:0] bus_miso_reg, bus_miso_next;
39 reg bus_busy_reg, bus_busy_next;
40
41 reg ram_wren_reg [2:0];
42 reg ram_wren_next [2:0];
43
44 reg [17:0] ram_data_reg, ram_data_next;
45 reg [19:0] ram_addr_reg, ram_addr_next;
46
47 wire [17:0] ram_wren_wire;
48
49 assign ram_wren = ~ram_wren_reg[0];
50 assign ram_addr = ram_addr_reg;
51
52 integer i;
53 genvar j;
54
55 generate
56 for (j = 0; j < 18; j = j + 1)
57 begin : SRAM_WREN
58 assign ram_wren_wire[j] = ram_wren_reg[2];
59 assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[j] : 1'bz;
60 end
61 endgenerate
62
63 always @(posedge clock)
[27]64 begin
65 if (reset)
[90]66 begin
67 osc_data_reg <= 48'd0;
68 ram_data_reg <= 18'd0;
69 ram_addr_reg <= 20'd0;
70 bus_miso_reg <= 16'd0;
71 bus_busy_reg <= 1'b0;
72 int_case_reg <= 5'd0;
73 int_cntr_reg <= 20'd0;
74 int_trig_reg <= 1'b0;
75 int_trig_addr_reg <= 20'd0;
76 cfg_cntr_max_reg <= 20'd0;
77 cfg_cntr_mid_reg <= 20'd0;
78
79 for(i = 0; i <= 2; i = i + 1)
80 begin
81 ram_wren_reg[i] <= 1'b0;
82 bus_mosi_reg[i] <= 16'd0;
83 end
[27]84 end
85 else
86 begin
[90]87 osc_data_reg <= osc_data_next;
88 ram_data_reg <= ram_data_next;
89 ram_addr_reg <= ram_addr_next;
90 bus_miso_reg <= bus_miso_next;
91 bus_busy_reg <= bus_busy_next;
92 int_case_reg <= int_case_next;
93 int_cntr_reg <= int_cntr_next;
94 int_trig_reg <= int_trig_next;
95 int_trig_addr_reg <= int_trig_addr_next;
96 cfg_cntr_max_reg <= cfg_cntr_max_next;
97 cfg_cntr_mid_reg <= cfg_cntr_mid_next;
98
99 for(i = 0; i <= 2; i = i + 1)
100 begin
101 ram_wren_reg[i] <= ram_wren_next[i];
102 bus_mosi_reg[i] <= bus_mosi_next[i];
103 end
[27]104 end
105 end
[90]106
[27]107
108 always @*
109 begin
110
[90]111 osc_data_next = osc_data_reg;
112 ram_data_next = ram_data_reg;
113 ram_addr_next = ram_addr_reg;
114 bus_miso_next = bus_miso_reg;
115 bus_busy_next = bus_busy_reg;
116 int_case_next = int_case_reg;
117 int_cntr_next = int_cntr_reg;
118 int_trig_next = int_trig_reg;
119 int_trig_addr_next = int_trig_addr_reg;
120 cfg_cntr_max_next = cfg_cntr_max_reg;
121 cfg_cntr_mid_next = cfg_cntr_mid_reg;
122
123 for(i = 0; i < 2; i = i + 1)
124 begin
125 ram_wren_next[i+1] = ram_wren_reg[i];
126 bus_mosi_next[i+1] = bus_mosi_reg[i];
127 end
128 ram_wren_next[0] = 1'b0;
129 bus_mosi_next[0] = 16'd0;
130
131 case (int_case_reg)
[51]132 0:
[27]133 begin
[90]134 ram_data_next = 18'd0;
135 ram_addr_next = 20'd0;
136 bus_busy_next = 1'b0;
137 int_cntr_next = 20'd0;
138 int_trig_next = 1'b0;
139
140 ram_data_next = {bus_mosi_reg[1][15:8], 1'b0, bus_mosi_reg[1][7:0], 1'b0};
141
142 if (bus_ssel)
[27]143 begin
[90]144 bus_miso_next = {ram_data[17:10], ram_data[8:1]};
145 ram_wren_next[0] = bus_wren;
146 if (bus_wren)
147 begin
148 ram_addr_next = bus_addr;
149 bus_mosi_next[0] = bus_mosi;
150 end
151 else
152 begin
153// ram_addr_next = int_trig_addr_reg + bus_addr;
154 ram_addr_next = bus_addr;
155 end
[27]156 end
[90]157 else if (cfg_data[16])
[27]158 begin
[90]159 // start recording
160 ram_wren_next[0] = 1'b1;
161 bus_busy_next = 1'b1;
162 int_case_next = 3'd1;
163 int_trig_addr_next = 20'd0;
164 cfg_cntr_max_next = {cfg_data[7:0], 10'd0};
165 cfg_cntr_mid_next = {cfg_data[15:8], 10'd0};
[27]166 end
[90]167
[27]168 end
[51]169
[90]170 // sample recording
171 1:
[27]172 begin
[90]173 ram_wren_next[0] = 1'b1;
174 if (frame)
[27]175 begin
[90]176 osc_data_next = osc_data;
177 ram_addr_next = ram_addr_reg + 20'd1;
178 int_case_next = 3'd2;
[51]179
[90]180 if ((~int_trig_reg) & (trg_flag) &
181 (int_cntr_reg == cfg_cntr_mid_reg))
[27]182 begin
[90]183 int_trig_next = 1'b1;
184 int_trig_addr_next = ram_addr_reg;
[27]185 end
[51]186
[90]187 if (int_trig_reg | (int_cntr_reg < cfg_cntr_mid_reg))
[51]188 begin
[90]189 int_cntr_next = int_cntr_reg + 20'd1;
[51]190 end
[27]191 end
192 end
193
[90]194 2:
[27]195 begin
[90]196 ram_wren_next[0] = 1'b1;
197 ram_data_next = {osc_data_reg[15:8], 1'b0, osc_data_reg[7:0], 1'b0};
198 ram_addr_next = ram_addr_reg + 20'd1;
199 int_case_next = 3'd3;
[27]200 end
[90]201
202 3:
203 begin
204 ram_wren_next[0] = 1'b1;
205 ram_data_next = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};
206 ram_addr_next = ram_addr_reg + 20'd1;
207 int_case_next = 3'd4;
208 end
209
210 4:
211 begin
212 ram_wren_next[0] = 1'b1;
213 ram_data_next = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
214 int_case_next = 3'd1;
215 if (int_cntr_reg >= cfg_cntr_max_reg)
216 begin
217 ram_wren_next[0] = 1'b0;
218 ram_addr_next = 20'd0;
219 int_case_next = 3'd0;
220 end
221 end
222
[27]223 endcase
224 end
225
[90]226 assign bus_miso = bus_miso_reg;
227 assign bus_busy = bus_busy_reg;
[27]228
229endmodule
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