Last change
on this file since 89 was 84, checked in by demin, 15 years ago |
improve timings in all components
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-
Property svn:executable
set to
*
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File size:
3.1 KB
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Rev | Line | |
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[66] | 1 | module i2c_fifo
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| 2 | (
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| 3 | input wire clk, aclr,
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| 4 | input wire wrreq,
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| 5 | input wire [15:0] data,
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| 6 | output wire full,
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| 7 |
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| 8 | inout wire i2c_sda,
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[71] | 9 | inout wire i2c_scl
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[66] | 10 | );
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| 11 |
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| 12 | wire int_rdempty, i2c_clk, start, stop;
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| 13 | wire [15:0] int_q;
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| 14 |
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| 15 | reg int_rdreq, int_clken, int_sdo, int_scl, int_ack;
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| 16 | reg [15:0] int_data;
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[84] | 17 | reg [9:0] counter;
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[66] | 18 | reg [4:0] state;
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| 19 |
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| 20 | assign i2c_sda = int_sdo ? 1'bz : 1'b0;
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[84] | 21 | assign i2c_scl = int_scl | (int_clken ? counter[9] : 1'b0);
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[66] | 22 |
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| 23 | assign start = int_data[8];
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| 24 | assign stop = int_data[9];
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| 25 |
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[71] | 26 | scfifo #(
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| 27 | .add_ram_output_register("OFF"),
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[66] | 28 | .intended_device_family("Cyclone III"),
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| 29 | .lpm_numwords(16),
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| 30 | .lpm_showahead("ON"),
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[71] | 31 | .lpm_type("scfifo"),
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[66] | 32 | .lpm_width(16),
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| 33 | .lpm_widthu(4),
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| 34 | .overflow_checking("ON"),
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| 35 | .underflow_checking("ON"),
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[84] | 36 | .use_eab("ON")) fifo_tx (
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[71] | 37 | .rdreq((~int_rdempty) & (int_rdreq) & (&counter)),
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[66] | 38 | .aclr(aclr),
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[71] | 39 | .clock(clk),
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| 40 | .wrreq(wrreq),
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[66] | 41 | .data(data),
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[71] | 42 | .empty(int_rdempty),
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[66] | 43 | .q(int_q),
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[71] | 44 | .full(full),
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| 45 | .almost_empty(),
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| 46 | .almost_full(),
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| 47 | .sclr(),
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| 48 | .usedw());
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[66] | 49 |
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| 50 | always @ (posedge clk)
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| 51 | begin
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[84] | 52 | counter <= counter + 10'd1;
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[71] | 53 | if (&counter)
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| 54 | begin
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| 55 | case (state)
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| 56 | 0:
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[66] | 57 | begin
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[71] | 58 | int_ack <= 1'b0;
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[66] | 59 | int_sdo <= 1'b1;
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| 60 | int_scl <= 1'b1;
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[71] | 61 | int_rdreq <= 1'b1;
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| 62 | state <= 5'd1;
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[66] | 63 | end
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[71] | 64 |
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| 65 | 1:
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[66] | 66 | begin
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[71] | 67 | if (~int_rdempty)
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| 68 | begin
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| 69 | int_data <= int_q;
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| 70 | int_rdreq <= 1'b0;
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| 71 | state <= 5'd2;
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| 72 | end
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[66] | 73 | end
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[71] | 74 |
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| 75 | 2:
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| 76 | begin
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| 77 | if (start)
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| 78 | begin
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| 79 | int_sdo <= 1'b1;
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| 80 | int_scl <= 1'b1;
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| 81 | state <= 5'd3;
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| 82 | end
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| 83 | else
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| 84 | begin
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| 85 | state <= 5'd5;
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| 86 | end
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| 87 | end
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[66] | 88 |
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[71] | 89 | 3:
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| 90 | begin // start
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| 91 | int_sdo <= 1'b0;
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| 92 | state <= 5'd4;
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| 93 | end
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| 94 |
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| 95 | 4:
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[66] | 96 | begin
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| 97 | int_scl <= 1'b0;
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[71] | 98 | state <= 5'd5;
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[66] | 99 | end
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[71] | 100 |
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| 101 | 5:
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| 102 | begin // data
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| 103 | int_clken <= 1'b1;
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| 104 | int_sdo <= int_data[7];
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[66] | 105 | state <= 5'd6;
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| 106 | end
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[71] | 107 |
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| 108 | 6:
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| 109 | begin
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| 110 | int_sdo <= int_data[6];
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| 111 | state <= 5'd7;
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| 112 | end
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| 113 |
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| 114 | 7:
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| 115 | begin
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| 116 | int_sdo <= int_data[5];
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| 117 | state <= 5'd8;
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| 118 | end
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| 119 |
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| 120 | 8:
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| 121 | begin
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| 122 | int_sdo <= int_data[4];
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| 123 | state <= 5'd9;
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| 124 | end
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| 125 |
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| 126 | 9:
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| 127 | begin
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| 128 | int_sdo <= int_data[3];
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| 129 | state <= 5'd10;
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| 130 | end
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| 131 |
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| 132 | 10:
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| 133 | begin
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| 134 | int_sdo <= int_data[2];
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| 135 | state <= 5'd11;
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| 136 | end
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| 137 |
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| 138 | 11:
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| 139 | begin
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| 140 | int_sdo <= int_data[1];
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| 141 | state <= 5'd12;
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| 142 | end
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| 143 |
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| 144 | 12:
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| 145 | begin
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| 146 | int_sdo <= int_data[0];
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| 147 | state <= 5'd13;
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| 148 | end
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| 149 |
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| 150 | 13:
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| 151 | begin // ack
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| 152 | int_sdo <= 1'b1;
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| 153 | int_rdreq <= 1'b1;
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| 154 | state <= 5'd14;
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| 155 | end
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| 156 |
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| 157 | 14:
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| 158 | begin
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| 159 | int_ack <= i2c_sda;
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| 160 | int_rdreq <= 1'b0;
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| 161 | if (stop | int_rdempty)
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| 162 | begin
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| 163 | int_clken <= 1'b0;
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| 164 | int_sdo <= 1'b0;
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| 165 | int_scl <= 1'b0;
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| 166 | state <= 5'd15;
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| 167 | end
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| 168 | else if (~int_rdempty)
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| 169 | begin
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| 170 | int_data <= int_q;
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| 171 | int_sdo <= int_q[7];
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| 172 | state <= 5'd6;
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| 173 | end
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| 174 | end
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| 175 |
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| 176 | 15:
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| 177 | begin // stop
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| 178 | int_scl <= 1'b1;
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| 179 | state <= 5'd16;
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| 180 | end
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| 181 |
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| 182 | 16:
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| 183 | begin
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| 184 | int_sdo <= 1'b1;
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| 185 | state <= 5'd0;
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| 186 | end
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| 187 |
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| 188 | endcase
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| 189 | end
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[66] | 190 | end
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| 191 |
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| 192 | endmodule
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