source: trunk/MultiChannelUSB/histogram.v@ 76

Last change on this file since 76 was 72, checked in by demin, 15 years ago

testing all components together

File size: 3.2 KB
Line 
1module histogram
2 #(
3 parameter W = 32 // bin resolution
4 )
5 (
6 input wire clk, reset,
7 input wire data_ready,
8 input wire [11:0] data, address,
9 output wire [W-1:0] q
10 );
11
12 // signal declaration
13 reg [3:0] state_reg, state_next;
14 reg flag_reg, flag_next;
15 reg wren_reg, wren_next;
16 reg [11:0] addr_reg, addr_next;
17 reg [W-1:0] data_reg, data_next;
18
19 wire [W-1:0] q_a_wire, q_b_wire;
20
21 wire [11:0] addr_wire;
22 wire [W-1:0] data_wire;
23
24 assign addr_wire = (flag_reg) ? data : addr_reg;
25 assign data_wire = (flag_reg) ? (q_a_wire + 32'd1) : data_reg;
26
27 altsyncram #(
28 .address_reg_b("CLOCK0"),
29 .clock_enable_input_a("BYPASS"),
30 .clock_enable_input_b("BYPASS"),
31 .clock_enable_output_a("BYPASS"),
32 .clock_enable_output_b("BYPASS"),
33 .indata_reg_b("CLOCK0"),
34 .intended_device_family("Cyclone III"),
35 .lpm_type("altsyncram"),
36 .numwords_a(4096),
37 .numwords_b(4096),
38 .operation_mode("BIDIR_DUAL_PORT"),
39 .outdata_aclr_a("NONE"),
40 .outdata_aclr_b("NONE"),
41 .outdata_reg_a("UNREGISTERED"),
42 .outdata_reg_b("UNREGISTERED"),
43 .power_up_uninitialized("FALSE"),
44 .read_during_write_mode_mixed_ports("OLD_DATA"),
45 .widthad_a(12),
46 .widthad_b(12),
47 .width_a(W),
48 .width_b(W),
49 .width_byteena_a(1),
50 .width_byteena_b(1),
51 .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
52 .wren_a(wren_reg),
53 .clock0(clk),
54 .wren_b(1'b0),
55 .address_a(addr_wire),
56 .address_b(address),
57 .data_a(data_wire),
58 .data_b(),
59 .q_a(q_a_wire),
60 .q_b(q_b_wire),
61 .aclr0(1'b0),
62 .aclr1(1'b0),
63 .addressstall_a(1'b0),
64 .addressstall_b(1'b0),
65 .byteena_a(1'b1),
66 .byteena_b(1'b1),
67 .clock1(1'b1),
68 .clocken0(1'b1),
69 .clocken1(1'b1),
70 .clocken2(1'b1),
71 .clocken3(1'b1),
72 .eccstatus(),
73 .rden_a(1'b1),
74 .rden_b(1'b1));
75
76 // body
77 always @(posedge clk)
78 begin
79 if (reset)
80 begin
81 flag_reg <= 1'b0;
82 wren_reg <= 1'b1;
83 addr_reg <= 12'd0;
84 data_reg <= 32'd0;
85 state_reg <= 4'b1;
86 end
87 else
88 begin
89 flag_reg <= flag_next;
90 wren_reg <= wren_next;
91 addr_reg <= addr_next;
92 data_reg <= data_next;
93 state_reg <= state_next;
94 end
95 end
96
97 always @*
98 begin
99 flag_next = flag_reg;
100 wren_next = wren_reg;
101 addr_next = addr_reg;
102 data_next = data_reg;
103 state_next = state_reg;
104 case (state_reg)
105 0:
106 begin
107 // nothing to do
108 flag_next = 1'b0;
109 wren_next = 1'b0;
110 addr_next = 12'd0;
111 data_next = 32'd0;
112 state_next = 4'd0;
113 end
114
115 1:
116 begin
117 // write zeros
118 if (&addr_reg)
119 begin
120 flag_next = 1'b1;
121 wren_next = 1'b0;
122 state_next = 4'd2;
123 end
124 else
125 begin
126 addr_next = addr_reg + 12'd1;
127 end
128 end
129
130 2:
131 begin
132 if (data_ready)
133 begin
134 if (&q_a_wire)
135 begin
136 flag_next = 1'b0;
137 state_next = 4'd0;
138 end
139 else
140 begin
141 wren_next = 1'b1;
142 state_next = 4'd3;
143 end
144 end
145 end
146
147 3:
148 begin
149 wren_next = 1'b0;
150 state_next = 4'd2;
151 end
152
153 default:
154 begin
155 flag_next = 1'b0;
156 wren_next = 1'b0;
157 addr_next = 12'd0;
158 data_next = 32'd0;
159 state_next = 4'd0;
160 end
161 endcase
162 end
163
164 // output logic
165 assign q = q_b_wire;
166endmodule
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