[27] | 1 | module histogram
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| 2 | (
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[90] | 3 | input wire clock, frame, reset,
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| 4 |
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| 5 | input wire [40:0] cfg_data,
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| 6 |
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| 7 | input wire hst_good,
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| 8 | input wire [11:0] hst_data,
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| 9 |
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| 10 | input wire bus_ssel, bus_wren,
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| 11 | input wire [12:0] bus_addr,
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| 12 | input wire [15:0] bus_mosi,
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| 13 |
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| 14 | output wire [15:0] bus_miso,
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| 15 | output wire bus_busy
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[27] | 16 | );
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| 17 |
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| 18 | // signal declaration
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[90] | 19 | reg [3:0] int_case_reg, int_case_next;
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| 20 | reg int_wren_reg, int_wren_next;
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| 21 | reg [11:0] int_addr_reg, int_addr_next;
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| 22 | reg [31:0] int_data_reg, int_data_next;
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[27] | 23 |
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[90] | 24 | reg [12:0] bus_addr_reg, bus_addr_next;
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| 25 | reg [15:0] bus_miso_reg, bus_miso_next;
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[27] | 26 |
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[90] | 27 | reg bus_wren_reg, bus_wren_next;
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| 28 | reg [15:0] bus_mosi_reg, bus_mosi_next;
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| 29 |
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| 30 | wire [31:0] q_a_wire;
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| 31 | wire [15:0] q_b_wire;
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| 32 |
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[47] | 33 | altsyncram #(
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| 34 | .address_reg_b("CLOCK0"),
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| 35 | .clock_enable_input_a("BYPASS"),
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| 36 | .clock_enable_input_b("BYPASS"),
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| 37 | .clock_enable_output_a("BYPASS"),
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| 38 | .clock_enable_output_b("BYPASS"),
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| 39 | .indata_reg_b("CLOCK0"),
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| 40 | .intended_device_family("Cyclone III"),
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| 41 | .lpm_type("altsyncram"),
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| 42 | .numwords_a(4096),
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[90] | 43 | .numwords_b(8192),
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[47] | 44 | .operation_mode("BIDIR_DUAL_PORT"),
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| 45 | .outdata_aclr_a("NONE"),
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| 46 | .outdata_aclr_b("NONE"),
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[84] | 47 | .outdata_reg_a("CLOCK0"),
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| 48 | .outdata_reg_b("CLOCK0"),
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[47] | 49 | .power_up_uninitialized("FALSE"),
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| 50 | .read_during_write_mode_mixed_ports("OLD_DATA"),
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[90] | 51 | .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
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| 52 | .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
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[47] | 53 | .widthad_a(12),
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[90] | 54 | .widthad_b(13),
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| 55 | .width_a(32),
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| 56 | .width_b(16),
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[47] | 57 | .width_byteena_a(1),
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| 58 | .width_byteena_b(1),
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[51] | 59 | .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
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[90] | 60 | .wren_a(int_wren_reg),
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| 61 | .clock0(clock),
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| 62 | .wren_b(bus_wren_reg),
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| 63 | .address_a(int_addr_reg),
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| 64 | .address_b(bus_addr_reg),
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| 65 | .data_a(int_data_reg),
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| 66 | .data_b(bus_mosi_reg),
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[51] | 67 | .q_a(q_a_wire),
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| 68 | .q_b(q_b_wire),
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| 69 | .aclr0(1'b0),
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| 70 | .aclr1(1'b0),
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| 71 | .addressstall_a(1'b0),
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| 72 | .addressstall_b(1'b0),
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| 73 | .byteena_a(1'b1),
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| 74 | .byteena_b(1'b1),
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| 75 | .clock1(1'b1),
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| 76 | .clocken0(1'b1),
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| 77 | .clocken1(1'b1),
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| 78 | .clocken2(1'b1),
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| 79 | .clocken3(1'b1),
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| 80 | .eccstatus(),
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| 81 | .rden_a(1'b1),
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| 82 | .rden_b(1'b1));
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[27] | 83 |
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| 84 | // body
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[90] | 85 | always @(posedge clock)
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[27] | 86 | begin
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| 87 | if (reset)
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| 88 | begin
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[90] | 89 | int_wren_reg <= 1'b1;
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| 90 | int_addr_reg <= 12'd0;
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| 91 | int_data_reg <= 32'd0;
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| 92 | int_case_reg <= 4'b1;
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| 93 | bus_addr_reg <= 13'd0;
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| 94 | bus_miso_reg <= 16'd0;
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| 95 | bus_wren_reg <= 1'b0;
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| 96 | bus_mosi_reg <= 16'd0;
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[27] | 97 | end
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| 98 | else
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| 99 | begin
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[90] | 100 | int_wren_reg <= int_wren_next;
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| 101 | int_addr_reg <= int_addr_next;
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| 102 | int_data_reg <= int_data_next;
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| 103 | int_case_reg <= int_case_next;
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| 104 | bus_addr_reg <= bus_addr_next;
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| 105 | bus_miso_reg <= bus_miso_next;
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| 106 | bus_wren_reg <= bus_wren_next;
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| 107 | bus_mosi_reg <= bus_mosi_next;
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| 108 | end
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| 109 | end
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| 110 |
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| 111 | always @*
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| 112 | begin
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| 113 | bus_addr_next = bus_addr_reg;
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| 114 | bus_miso_next = bus_miso_reg;
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| 115 |
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| 116 | bus_wren_next = 1'b0;
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| 117 | bus_mosi_next = bus_mosi_reg;
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| 118 |
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| 119 | if (bus_ssel)
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| 120 | begin
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| 121 | bus_miso_next = q_b_wire;
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| 122 | bus_addr_next = bus_addr;
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| 123 | bus_wren_next = bus_wren;
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| 124 | if (bus_wren)
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| 125 | begin
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| 126 | bus_mosi_next = bus_mosi;
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| 127 | end
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[27] | 128 | end
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| 129 | end
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| 130 |
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| 131 | always @*
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| 132 | begin
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[90] | 133 | int_wren_next = int_wren_reg;
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| 134 | int_addr_next = int_addr_reg;
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| 135 | int_data_next = int_data_reg;
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| 136 | int_case_next = int_case_reg;
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| 137 |
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| 138 | case (int_case_reg)
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[51] | 139 | 0:
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[27] | 140 | begin
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[90] | 141 | int_wren_next = 1'b0;
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| 142 | int_addr_next = 12'd0;
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| 143 | int_data_next = 32'd0;
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[27] | 144 | end
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[51] | 145 |
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| 146 | 1:
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[27] | 147 | begin
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| 148 | // write zeros
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[90] | 149 | if (&int_addr_reg)
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[27] | 150 | begin
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[90] | 151 | int_wren_next = 1'b0;
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| 152 | int_case_next = 4'd2;
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[27] | 153 | end
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| 154 | else
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| 155 | begin
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[90] | 156 | int_addr_next = int_addr_reg + 12'd1;
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[27] | 157 | end
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[51] | 158 | end
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| 159 |
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| 160 | 2:
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[27] | 161 | begin
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[90] | 162 | int_wren_next = 1'b0;
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| 163 | if (&int_data_reg)
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[27] | 164 | begin
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[90] | 165 | int_case_next = 4'd0;
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[27] | 166 | end
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[90] | 167 | else if (frame & hst_good)
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| 168 | begin
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| 169 | int_addr_next = hst_data;
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| 170 | int_case_next = 4'd3;
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| 171 | end
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[27] | 172 | end
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| 173 |
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[51] | 174 | 3:
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[27] | 175 | begin
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[90] | 176 | int_case_next = 4'd4;
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[27] | 177 | end
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| 178 |
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[84] | 179 | 4:
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| 180 | begin
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[90] | 181 | int_case_next = 4'd5;
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[88] | 182 | end
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| 183 |
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| 184 | 5:
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| 185 | begin
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[90] | 186 | int_wren_next = 1'b1;
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| 187 | int_data_next = q_a_wire + 32'd1;
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| 188 | int_case_next = 4'd2;
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[84] | 189 | end
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| 190 |
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[27] | 191 | default:
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| 192 | begin
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[90] | 193 | int_wren_next = 1'b0;
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| 194 | int_addr_next = 12'd0;
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| 195 | int_data_next = 32'd0;
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| 196 | int_case_next = 4'd0;
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[27] | 197 | end
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| 198 | endcase
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| 199 | end
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| 200 |
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| 201 | // output logic
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[90] | 202 | assign bus_miso = bus_miso_reg;
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| 203 | assign bus_busy = 1'b0;
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[27] | 204 | endmodule
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