source: trunk/MultiChannelUSB/control.v@ 84

Last change on this file since 84 was 84, checked in by demin, 15 years ago

improve timings in all components
File size: 9.4 KB
RevLine 
[59]1module control
2 (
3 input wire clk,
[72]4
5 output wire cfg_reset,
6 input wire [15:0] cfg_src_data,
7 output wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr,
8
[59]9 input wire rx_empty, tx_full,
10 input wire [7:0] rx_data,
[69]11
[59]12 input wire [1:0] mux_max_byte,
13 input wire [15:0] mux_min_addr, mux_max_addr,
14 input wire [7:0] mux_q,
15
16 output wire mux_reset,
17 output wire mux_type,
18 output wire [1:0] mux_chan,
19 output wire [1:0] mux_byte,
20 output wire [15:0] mux_addr,
[69]21
[59]22 output wire rx_rdreq,
23 output wire tx_wrreq,
24 output wire [7:0] tx_data,
[69]25
[65]26 output wire ram_we,
27 output wire [19:0] ram_addr,
28 inout wire [17:0] ram_data,
[69]29
[84]30 input wire ept_data_ready,
31 input wire [47:0] ept_data,
32
[69]33 output wire i2c_wrreq,
34 output wire [15:0] i2c_data,
35 input wire i2c_full,
36
[59]37 output wire led
38 );
39
[65]40 reg [23:0] led_counter;
[84]41 reg [19:0] ram_counter;
[59]42 reg [10:0] tst_counter;
43 reg [15:0] int_addr, int_max_addr;
44
45 reg int_rdreq, int_wrreq;
46 reg int_type, int_reset;
47 reg [1:0] int_chan, int_byte, int_max_byte;
48 reg [7:0] int_data;
49 reg int_led;
50
[69]51 reg [15:0] int_i2c_data;
52 reg int_i2c_wrreq;
[59]53
[84]54 reg [47:0] int_ept_data;
55
[72]56 reg int_cfg_reset;
57 reg [15:0] int_dst_data, int_dst_addr;
[69]58
[65]59 wire crc_error = 1'b0;
60 reg crc_reset;
[79]61 reg [1:0] byte_counter;
[65]62 reg [4:0] idle_counter;
63
[69]64 reg [4:0] state;
[65]65
66 wire [15:0] src, dst;
[59]67
[79]68 reg [7:0] buffer [3:0];
[65]69
[72]70 assign src = (buffer[0][7]) ? cfg_src_data : {buffer[2], buffer[3]};
[65]71 assign dst = {1'b0, buffer[0][6:0], buffer[1]};
72
73 reg int_ram_we;
74 reg [17:0] int_ram_data;
75 wire [17:0] int_ram_q;
76 wire [17:0] opt_ram_we;
77 assign ram_we = ~int_ram_we;
78 assign int_ram_q = ram_data;
79// assign ram_data = int_ram_we ? int_ram_data : 18'bz;
[69]80// assign ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]};
[84]81 assign ram_addr = ram_counter;
[65]82
83 genvar j;
84 generate
85 for (j = 0; j < 18; j = j + 1)
86 begin : SRAM_WE
87 assign opt_ram_we[j] = int_ram_we;
88 assign ram_data[j] = opt_ram_we[j] ? int_ram_data[j] : 1'bz;
89 end
90 endgenerate
91
[59]92 always @(posedge clk)
93 begin
94 if (~rx_empty)
95 begin
96 int_led <= 1'b0;
[65]97 led_counter <= 24'd0;
[59]98 end
99 else
100 begin
[65]101 if (&led_counter)
[59]102 begin
103 int_led <= 1'b1;
104 end
105 else
106 begin
[65]107 led_counter <= led_counter + 24'd1;
[59]108 end
109 end
110
111 case(state)
[65]112 0:
[59]113 begin
114 int_rdreq <= 1'b1;
115 int_wrreq <= 1'b0;
116 int_type <= 1'b0;
117 int_chan <= 2'd0;
118 int_byte <= 2'd0;
119 int_reset <= 1'b0;
[65]120 crc_reset <= 1'b0;
121 int_ram_we <= 1'b0;
122 int_ram_data <= 16'd0;
[84]123 ram_counter <= 20'd0;
[65]124 idle_counter <= 5'd0;
[79]125 byte_counter <= 2'd0;
[72]126 int_cfg_reset <= 1'b0;
[69]127 state <= 5'd1;
[59]128 end
129
[65]130 1:
[59]131 begin
[65]132 // read 8 bytes
[59]133 if (~rx_empty)
134 begin
[65]135 idle_counter <= 5'd0;
[79]136 byte_counter <= byte_counter + 2'd1;
[65]137 buffer[byte_counter] <= rx_data;
138 if (&byte_counter)
139 begin
140 int_rdreq <= 1'b0;
[69]141 state <= 5'd2;
[65]142 end
143 end
144 else if(|byte_counter)
145 begin
146 idle_counter <= idle_counter + 5'd1;
147 if (&idle_counter)
148 begin
149 int_rdreq <= 1'b0;
150 crc_reset <= 1'b1;
[69]151 state <= 5'd0;
[65]152 end
153 end
154 end
155
156 2:
157 begin
158 crc_reset <= 1'b1;
159 if (~crc_error)
160 begin
[72]161 int_dst_addr <= dst;
162 int_dst_data <= src;
163// memory[dst[3:0]] <= src;
[65]164
165 case (dst)
166 16'h0000:
[59]167 begin
[72]168 int_cfg_reset <= 1'b1;
[69]169 state <= 5'd0;
[59]170 end
171
[65]172 16'h0001:
[59]173 begin
[65]174 int_type <= src[4];
175 int_chan <= src[1:0];
176 int_reset <= 1'b1;
[69]177 state <= 5'd0;
[59]178 end
179
[65]180 16'h0002:
[59]181 begin
[65]182 int_type <= src[4];
183 int_chan <= src[1:0];
[69]184 state <= 5'd3;
[59]185 end
186
[65]187 16'h0003:
[59]188 begin
189 tst_counter <= 11'd0;
[84]190 state <= 5'd7;
[59]191 end
[65]192 16'h0004:
193 begin
194 int_ram_we <= 1'b1;
195 int_ram_data <= 18'd0;
[84]196 ram_counter <= 20'd0;
197 state <= 5'd10;
[65]198 end
[69]199 16'h0005:
200 begin
201 int_i2c_data <= src;
202 int_i2c_wrreq <= 1'b1;
[84]203 state <= 5'd16;
[69]204 end
[84]205 16'h0006:
206 begin
207 int_ram_we <= 1'b1;
208 int_ram_data <= 18'd0;
209 ram_counter <= 20'd0;
210 state <= 5'd17;
211 end
[72]212
213 default:
214 begin
215 state <= 5'd0;
216 end
[59]217 endcase
218 end
219 end
[65]220
[59]221 // mux transfer
222 3:
223 begin
[65]224 crc_reset <= 1'b0;
[59]225 int_addr <= mux_min_addr;
226 int_max_addr <= mux_min_addr + mux_max_addr;
227 int_max_byte <= mux_max_byte;
228 int_byte <= 2'd0;
[69]229 state <= 5'd4;
[59]230 end
231
232 4:
233 begin
234 int_wrreq <= 1'b0;
[69]235 state <= 5'd5;
[59]236 end
237
238 5:
239 begin
[84]240 state <= 5'd6;
241 end
242
243 6:
244 begin
[59]245 if (~tx_full)
246 begin
247 int_data <= mux_q;
248 int_wrreq <= 1'b1;
249 if ((int_byte == int_max_byte) && (int_addr == int_max_addr))
250 begin
[69]251 state <= 5'd0;
[59]252 end
253 else
254 begin
[69]255 state <= 5'd4;
[59]256 if (int_byte == int_max_byte)
257 begin
258 int_addr <= int_addr + 16'd1;
259 int_byte <= 2'd0;
260 end
261 else
262 begin
263 int_byte <= int_byte + 2'd1;
264 end
265 end
266 end
267 end
268
269 // tst transfer
[84]270 7:
[59]271 begin
[65]272 crc_reset <= 1'b0;
[59]273 int_data <= tst_counter;
274 int_wrreq <= 1'b1;
275 tst_counter <= tst_counter + 11'd1;
[84]276 state <= 5'd8;
[59]277 end
[84]278 8:
[59]279 begin
280 if (~tx_full)
281 begin
282 int_data <= tst_counter;
[65]283 if (&tst_counter)
[59]284 begin
[84]285 state <= 5'd9;
[59]286 end
287 else
288 begin
289 tst_counter <= tst_counter + 11'd1;
290 end
291 end
292 end
[84]293 9:
[59]294 begin
295 if (~tx_full)
296 begin
297 int_wrreq <= 1'b0;
[69]298 state <= 5'd0;
[59]299 end
300 end
[65]301 // ram transfer
[84]302 10:
[65]303 begin
304 crc_reset <= 1'b0;
[84]305 state <= 5'd11;
[65]306 end
[84]307 11:
[65]308 begin
309 int_ram_data[8:1] <= ram_counter[7:0];
310// int_ram_data[8:1] <= 8'd0;
[84]311 if (&ram_counter[18:0])
[65]312 begin
[84]313 state <= 5'd12;
[65]314 end
315 else
316 begin
[84]317 state <= 5'd10;
318 ram_counter <= ram_counter + 20'd1;
[65]319 end
320 end
[84]321 12:
[65]322 begin
323 int_ram_we <= 1'b0;
324 int_ram_data <= 18'd0;
[84]325 ram_counter <= 20'd0;
[69]326 state <= 5'd13;
[65]327 end
328 13:
329 begin
[84]330 int_wrreq <= 1'b0;
[69]331 state <= 5'd14;
[65]332 end
333 14:
334 begin
[84]335 state <= 5'd15;
336 end
337 15:
338 begin
[65]339 if (~tx_full)
340 begin
341 int_data <= int_ram_q[8:1];
342 int_wrreq <= 1'b1;
[84]343 if (&ram_counter[18:0])
[65]344 begin
[69]345 state <= 5'd0;
[65]346 end
347 else
348 begin
[84]349 state <= 5'd13;
350 ram_counter <= ram_counter + 20'd1;
[65]351 end
352 end
353 end
[59]354
[69]355 // i2c write
[84]356 16:
[69]357 begin
358 crc_reset <= 1'b0;
359 if (~i2c_full)
360 begin
361 int_i2c_wrreq <= 1'b0;
362 state <= 5'd0;
363 end
364 end
365
[84]366 // long sample transfer
367 17:
368 begin
369 crc_reset <= 1'b0;
370 if (ept_data_ready)
371 begin
372 ram_counter <= ram_counter + 20'd1;
373 int_ept_data <= ept_data;
374 state <= 5'd18;
375 end
376 end
377 18:
378 begin
379// int_ram_data[8:1] <= ram_counter[7:0];
380 int_ram_data[8:1] <= int_ept_data[7:0];
381 int_ram_data[17:10] <= int_ept_data[15:8];
382 ram_counter <= ram_counter + 20'd1;
383 state <= 5'd19;
384 end
385 19:
386 begin
387// int_ram_data[8:1] <= ram_counter[7:0];
388 int_ram_data[8:1] <= int_ept_data[23:16];
389 int_ram_data[17:10] <= int_ept_data[31:24];
390 ram_counter <= ram_counter + 20'd1;
391 state <= 5'd20;
392 end
393
394 20:
395 begin
396// int_ram_data[8:1] <= ram_counter[7:0];
397 int_ram_data[8:1] <= int_ept_data[39:32];
398 int_ram_data[17:10] <= int_ept_data[47:40];
399 if (&ram_counter)
400 begin
401 int_ram_we <= 1'b0;
402 int_ram_data <= 18'd0;
403 ram_counter <= 19'd0;
404 state <= 5'd21;
405 end
406 else
407 begin
408 state <= 5'd17;
409 end
410 end
411/*
412 21:
413 begin
414 int_wrreq <= 1'b0;
415 state <= 5'd22;
416 end
417
418 22:
419 begin
420 state <= 5'd23;
421 end
422
423 23:
424 begin
425 if (~tx_full)
426 begin
427 int_data <= int_ram_q[8:1];
428 int_wrreq <= 1'b1;
429 if (&ram_counter)
430 begin
431 state <= 5'd0;
432 end
433 else
434 begin
435 state <= 5'd21;
436 ram_counter <= ram_counter + 20'd1;
437 end
438 end
439 end
440*/
441 21:
442 begin
443 int_wrreq <= 1'b0;
444 state <= 5'd22;
445 end
446
447 22:
448 begin
449 state <= 5'd23;
450 end
451
452 23:
453 begin
454 if (~tx_full)
455 begin
456 int_data <= int_ram_q[8:1];
457 int_wrreq <= 1'b1;
458 state <= 5'd24;
459 end
460 end
461
462 24:
463 begin
464 int_data <= int_ram_q[17:10];
465 state <= 5'd25;
466 end
467
468 25:
469 begin
470 if (~tx_full)
471 begin
472 int_wrreq <= 1'b0;
473 if (&ram_counter)
474 begin
475 state <= 5'd0;
476 end
477 else
478 begin
479 state <= 5'd21;
480 ram_counter <= ram_counter + 20'd1;
481 end
482 end
483 end
484
[59]485 default:
486 begin
[69]487 state <= 5'd0;
[59]488 end
489 endcase
490 end
491
[72]492 assign cfg_reset = int_cfg_reset;
493 assign cfg_src_addr = {buffer[2], buffer[3]};
494 assign cfg_dst_data = int_dst_data;
495 assign cfg_dst_addr = int_dst_addr;
[59]496 assign mux_reset = int_reset;
497 assign mux_type = int_type;
498 assign mux_chan = int_chan;
499 assign mux_byte = int_byte;
500 assign mux_addr = int_addr;
501 assign rx_rdreq = int_rdreq & (~rx_empty);
502 assign tx_wrreq = int_wrreq & (~tx_full);
503 assign tx_data = int_data;
[69]504 assign i2c_wrreq = int_i2c_wrreq;
505 assign i2c_data = int_i2c_data;
[59]506 assign led = int_led;
507
508endmodule
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