source: trunk/MultiChannelUSB/control.v@ 71

Last change on this file since 71 was 69, checked in by demin, 15 years ago

add I2C master
File size: 6.5 KB
RevLine 
[59]1module control
2 (
3 input wire clk,
4 input wire rx_empty, tx_full,
5 input wire [7:0] rx_data,
[69]6
[59]7 input wire [1:0] mux_max_byte,
8 input wire [15:0] mux_min_addr, mux_max_addr,
9 input wire [7:0] mux_q,
10
11 output wire mux_reset,
12 output wire mux_type,
13 output wire [1:0] mux_chan,
14 output wire [1:0] mux_byte,
15 output wire [15:0] mux_addr,
[69]16
[59]17 output wire rx_rdreq,
18 output wire tx_wrreq,
19 output wire [7:0] tx_data,
[69]20
[65]21 output wire ram_we,
22 output wire [19:0] ram_addr,
23 inout wire [17:0] ram_data,
[69]24
25 output wire i2c_wrreq,
26 output wire [15:0] i2c_data,
27 input wire i2c_full,
28
[59]29 output wire led
30 );
31
[65]32 reg [23:0] led_counter;
33 reg [18:0] ram_counter;
[59]34 reg [10:0] tst_counter;
35 reg [15:0] int_addr, int_max_addr;
36
37 reg int_rdreq, int_wrreq;
38 reg int_type, int_reset;
39 reg [1:0] int_chan, int_byte, int_max_byte;
40 reg [7:0] int_data;
41 reg int_led;
42
[69]43 reg [15:0] int_i2c_data;
44 reg int_i2c_wrreq;
[59]45
[69]46
[65]47 wire crc_error = 1'b0;
48 reg crc_reset;
49 reg [2:0] byte_counter;
50 reg [4:0] idle_counter;
51
[69]52 reg [4:0] state;
[65]53
54 wire [15:0] src, dst;
[59]55
[65]56 reg [15:0] memory [15:0];
57 reg [7:0] buffer [7:0];
58
59 assign src = (buffer[0][7]) ? memory[buffer[3][3:0]] : {buffer[2], buffer[3]};
60 assign dst = {1'b0, buffer[0][6:0], buffer[1]};
61
62 reg int_ram_we;
63 reg [17:0] int_ram_data;
64 wire [17:0] int_ram_q;
65 wire [17:0] opt_ram_we;
66 assign ram_we = ~int_ram_we;
67 assign int_ram_q = ram_data;
68// assign ram_data = int_ram_we ? int_ram_data : 18'bz;
[69]69// assign ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]};
70 assign ram_addr = {1'd0, ram_counter[18:0]};
[65]71
72 genvar j;
73 generate
74 for (j = 0; j < 18; j = j + 1)
75 begin : SRAM_WE
76 assign opt_ram_we[j] = int_ram_we;
77 assign ram_data[j] = opt_ram_we[j] ? int_ram_data[j] : 1'bz;
78 end
79 endgenerate
80
[59]81 always @(posedge clk)
82 begin
83 if (~rx_empty)
84 begin
85 int_led <= 1'b0;
[65]86 led_counter <= 24'd0;
[59]87 end
88 else
89 begin
[65]90 if (&led_counter)
[59]91 begin
92 int_led <= 1'b1;
93 end
94 else
95 begin
[65]96 led_counter <= led_counter + 24'd1;
[59]97 end
98 end
99
100 case(state)
[65]101 0:
[59]102 begin
103 int_rdreq <= 1'b1;
104 int_wrreq <= 1'b0;
105 int_type <= 1'b0;
106 int_chan <= 2'd0;
107 int_byte <= 2'd0;
108 int_reset <= 1'b0;
[65]109 crc_reset <= 1'b0;
110 int_ram_we <= 1'b0;
111 int_ram_data <= 16'd0;
112 ram_counter <= 19'd0;
113 idle_counter <= 5'd0;
114 byte_counter <= 3'd0;
[69]115 state <= 5'd1;
[59]116 end
117
[65]118 1:
[59]119 begin
[65]120 // read 8 bytes
[59]121 if (~rx_empty)
122 begin
[65]123 idle_counter <= 5'd0;
124 byte_counter <= byte_counter + 3'd1;
125 buffer[byte_counter] <= rx_data;
126 if (&byte_counter)
127 begin
128 int_rdreq <= 1'b0;
[69]129 state <= 5'd2;
[65]130 end
131 end
132 else if(|byte_counter)
133 begin
134 idle_counter <= idle_counter + 5'd1;
135 if (&idle_counter)
136 begin
137 int_rdreq <= 1'b0;
138 crc_reset <= 1'b1;
[69]139 state <= 5'd0;
[65]140 end
141 end
142 end
143
144 2:
145 begin
146 crc_reset <= 1'b1;
147 if (~crc_error)
148 begin
149 memory[dst[3:0]] <= src;
150
151 case (dst)
152 16'h0000:
[59]153 begin
[69]154 state <= 5'd0;
[59]155 end
156
[65]157 16'h0001:
[59]158 begin
[65]159 int_type <= src[4];
160 int_chan <= src[1:0];
161 int_reset <= 1'b1;
[69]162 state <= 5'd0;
[59]163 end
164
[65]165 16'h0002:
[59]166 begin
[65]167 int_type <= src[4];
168 int_chan <= src[1:0];
[69]169 state <= 5'd3;
[59]170 end
171
[65]172 16'h0003:
[59]173 begin
174 tst_counter <= 11'd0;
[69]175 state <= 5'd6;
[59]176 end
[65]177 16'h0004:
178 begin
179 int_ram_we <= 1'b1;
180 int_ram_data <= 18'd0;
181 ram_counter <= 19'd0;
[69]182 state <= 5'd9;
[65]183 end
[69]184 16'h0005:
185 begin
186 int_i2c_data <= src;
187 int_i2c_wrreq <= 1'b1;
188 state <= 5'd15;
189 end
[59]190 endcase
191 end
192 end
[65]193
[59]194 // mux transfer
195 3:
196 begin
[65]197 crc_reset <= 1'b0;
[59]198 int_addr <= mux_min_addr;
199 int_max_addr <= mux_min_addr + mux_max_addr;
200 int_max_byte <= mux_max_byte;
201 int_byte <= 2'd0;
[69]202 state <= 5'd4;
[59]203 end
204
205 4:
206 begin
207 int_wrreq <= 1'b0;
[69]208 state <= 5'd5;
[59]209 end
210
211 5:
212 begin
213 if (~tx_full)
214 begin
215 int_data <= mux_q;
216 int_wrreq <= 1'b1;
217 if ((int_byte == int_max_byte) && (int_addr == int_max_addr))
218 begin
[69]219 state <= 5'd0;
[59]220 end
221 else
222 begin
[69]223 state <= 5'd4;
[59]224 if (int_byte == int_max_byte)
225 begin
226 int_addr <= int_addr + 16'd1;
227 int_byte <= 2'd0;
228 end
229 else
230 begin
231 int_byte <= int_byte + 2'd1;
232 end
233 end
234 end
235 end
236
237 // tst transfer
238 6:
239 begin
[65]240 crc_reset <= 1'b0;
[59]241 int_data <= tst_counter;
242 int_wrreq <= 1'b1;
243 tst_counter <= tst_counter + 11'd1;
[69]244 state <= 5'd7;
[59]245 end
246 7:
247 begin
248 if (~tx_full)
249 begin
250 int_data <= tst_counter;
[65]251 if (&tst_counter)
[59]252 begin
[69]253 state <= 5'd8;
[59]254 end
255 else
256 begin
257 tst_counter <= tst_counter + 11'd1;
258 end
259 end
260 end
261 8:
262 begin
263 if (~tx_full)
264 begin
265 int_wrreq <= 1'b0;
[69]266 state <= 5'd0;
[59]267 end
268 end
[65]269 // ram transfer
270 9:
271 begin
272 crc_reset <= 1'b0;
[69]273 state <= 5'd10;
[65]274 end
275 10:
276 begin
277 int_ram_data[8:1] <= ram_counter[7:0];
278// int_ram_data[8:1] <= 8'd0;
279 if (&ram_counter)
280 begin
[69]281 state <= 5'd11;
[65]282 end
283 else
284 begin
[69]285 state <= 5'd9;
[65]286 ram_counter <= ram_counter + 19'd1;
287 end
288 end
289 11:
290 begin
291 int_ram_we <= 1'b0;
292 int_ram_data <= 18'd0;
293 ram_counter <= 19'd0;
[69]294 state <= 5'd12;
[65]295 end
296 12:
297 begin
298 int_wrreq <= 1'b0;
[69]299 state <= 5'd13;
[65]300 end
301 13:
302 begin
[69]303 state <= 5'd14;
[65]304 end
305 14:
306 begin
307 if (~tx_full)
308 begin
309 int_data <= int_ram_q[8:1];
310 int_wrreq <= 1'b1;
311 if (&ram_counter)
312 begin
[69]313 state <= 5'd0;
[65]314 end
315 else
316 begin
[69]317 state <= 5'd12;
[65]318 ram_counter <= ram_counter + 19'd1;
319 end
320 end
321 end
[59]322
[69]323 // i2c write
324 15:
325 begin
326 crc_reset <= 1'b0;
327 if (~i2c_full)
328 begin
329 int_i2c_wrreq <= 1'b0;
330 state <= 5'd0;
331 end
332 end
333
[59]334 default:
335 begin
[69]336 state <= 5'd0;
[59]337 end
338 endcase
339 end
340
341 assign mux_reset = int_reset;
342 assign mux_type = int_type;
343 assign mux_chan = int_chan;
344 assign mux_byte = int_byte;
345 assign mux_addr = int_addr;
346 assign rx_rdreq = int_rdreq & (~rx_empty);
347 assign tx_wrreq = int_wrreq & (~tx_full);
348 assign tx_data = int_data;
[69]349 assign i2c_wrreq = int_i2c_wrreq;
350 assign i2c_data = int_i2c_data;
[59]351 assign led = int_led;
352
353endmodule
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