source: trunk/MultiChannelUSB/analyser.v@ 92

Last change on this file since 92 was 90, checked in by demin, 15 years ago

full rewrite

File size: 2.5 KB
Line 
1module analyser
2 (
3 input wire clock, frame, reset,
4 input wire [12:0] cfg_data,
5 input wire [1:0] uwt_flag,
6 input wire [11:0] uwt_data,
7 output wire ana_good,
8 output wire [11:0] ana_data,
9 output wire [11:0] ana_base
10 );
11
12 reg state_reg, state_next;
13 reg [4:0] counter_reg, counter_next;
14 reg good_reg, good_next;
15 reg [11:0] data_reg, data_next;
16
17 reg [19:0] buffer_reg [31:0];
18 reg [19:0] buffer_next [31:0];
19
20 wire [19:0] sample = {8'd0, uwt_data};
21 wire [11:0] baseline = buffer_reg[31][16:5];
22 wire counter_max = (&counter_reg);
23
24 integer i;
25
26 always @(posedge clock)
27 begin
28 if (reset)
29 begin
30 state_reg <= 1'b0;
31 counter_reg <= 5'd0;
32 good_reg <= 1'b0;
33 data_reg <= 12'd0;
34 for(i = 0; i <= 31; i = i + 1)
35 begin
36 buffer_reg[i] <= 20'hfffff;
37 end
38 end
39 else
40 begin
41 state_reg <= state_next;
42 counter_reg <= counter_next;
43 good_reg <= good_next;
44 data_reg <= data_next;
45
46 for(i = 0; i <= 31; i = i + 1)
47 begin
48 buffer_reg[i] <= buffer_next[i];
49 end
50 end
51 end
52
53 always @*
54 begin
55 state_next = state_reg;
56 counter_next = counter_reg;
57 good_next = good_reg;
58 data_next = data_reg;
59
60 for(i = 0; i <= 31; i = i + 1)
61 begin
62 buffer_next[i] = buffer_reg[i];
63 end
64
65 case (state_reg)
66 0: // skip first 32 samples
67 begin
68 if (frame)
69 begin
70 counter_next = counter_reg + 5'd1;
71 if (counter_max)
72 begin
73 state_next = 1'b1;
74 end
75 end
76 end
77
78 1:
79 begin
80 if (frame)
81 begin
82
83 if (cfg_data[12])
84 begin
85 if (uwt_data > baseline)
86 begin
87 data_next = uwt_data - baseline;
88 end
89 else
90 begin
91 data_next = 12'd0;
92 end
93 end
94 else
95 begin
96 if (uwt_data > cfg_data[11:0])
97 begin
98 data_next = uwt_data - cfg_data[11:0];
99 end
100 else
101 begin
102 data_next = 12'd0;
103 end
104 end
105
106
107 for(i = 0; i < 31; i = i + 1)
108 begin
109 buffer_next[i+1] = buffer_reg[i] + sample;
110 end
111 buffer_next[0] = sample;
112
113 good_next = uwt_flag[0] & counter_max;
114
115 // skip first 32 baseline samples
116 // skip 32 samples after peak
117 if (counter_max)
118 begin
119 if (uwt_flag[0])
120 begin
121 counter_next = 5'd0;
122 end
123 end
124 else
125 begin
126 counter_next = counter_reg + 5'd1;
127 end
128 end
129 end
130 endcase
131 end
132
133 assign ana_good = good_reg;
134 assign ana_data = data_reg;
135 assign ana_base = baseline;
136
137endmodule
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