source: trunk/MultiChannelUSB/analyser.v@ 74

Last change on this file since 74 was 72, checked in by demin, 15 years ago

testing all components together

File size: 1.8 KB
Line 
1module analyser
2 (
3 input wire clk, reset,
4 input wire data_ready,
5 input wire [1:0] uwt_flag,
6 input wire [11:0] uwt_data,
7 output wire peak_ready,
8 output wire [11:0] peak
9 );
10
11 reg [1:0] state_reg, state_next;
12 reg [3:0] counter_reg, counter_next;
13 reg peak_ready_reg, peak_ready_next;
14 reg [11:0] peak_reg, peak_next;
15
16 always @(posedge clk)
17 begin
18 if (reset)
19 begin
20 state_reg <= 2'd0;
21 counter_reg <= 4'd0;
22 peak_ready_reg <= 1'b0;
23 peak_reg <= 12'd0;
24 end
25 else
26 begin
27 state_reg <= state_next;
28 counter_reg <= counter_next;
29 peak_ready_reg <= peak_ready_next;
30 peak_reg <= peak_next;
31 end
32 end
33
34 always @*
35 begin
36 state_next = state_reg;
37 counter_next = counter_reg;
38 peak_ready_next = peak_ready_reg;
39 peak_next = peak_reg;
40 case (state_reg)
41 0: // skip first 16 samples
42 begin
43 peak_next = 12'd0;
44 peak_ready_next = 1'b0;
45 if (data_ready)
46 begin
47 counter_next = counter_reg + 4'd1;
48 if (&counter_reg)
49 begin
50 state_next = 2'd1;
51 end
52 end
53 end
54
55 1: // skip first 16 minima
56 begin
57 if (data_ready & uwt_flag[1])
58 begin
59 counter_next = counter_reg + 4'd1;
60 if (&counter_reg)
61 begin
62 state_next = 2'd2;
63 end
64 end
65 end
66
67 2: // calculate peak height
68 begin
69 if (data_ready & uwt_flag[0])
70 begin
71 peak_next = uwt_data;
72 peak_ready_next = 1'b1;
73 end
74 else
75 begin
76 peak_ready_next = 1'b0;
77 end
78 end
79
80 default:
81 begin
82 peak_next = 12'd0;
83 peak_ready_next = 1'b0;
84 state_next = 2'd0;
85 end
86 endcase
87 end
88
89 assign peak_ready = peak_ready_reg;
90 assign peak = peak_reg;
91endmodule
Note: See TracBrowser for help on using the repository browser.