source:
trunk/MultiChannelUSB/analyser.v@
89
Last change on this file since 89 was 89, checked in by , 15 years ago | |
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File size: 1.7 KB |
Rev | Line | |
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[44] | 1 | module analyser |
2 | ( | |
3 | input wire clk, reset, | |
4 | input wire data_ready, | |
5 | input wire [1:0] uwt_flag, | |
[89] | 6 | output wire peak_ready |
[44] | 7 | ); |
8 | ||
[84] | 9 | reg flag_reg, flag_next; |
[44] | 10 | reg [1:0] state_reg, state_next; |
[84] | 11 | reg [4:0] counter_reg, counter_next; |
12 | reg peak_ready_reg; | |
[44] | 13 | |
[76] | 14 | wire counter_max = (&counter_reg); |
[84] | 15 | wire peak_ready_int = (flag_reg & data_ready & uwt_flag[0] & counter_max); |
[76] | 16 | |
[44] | 17 | always @(posedge clk) |
18 | begin | |
19 | if (reset) | |
20 | begin | |
[84] | 21 | flag_reg <= 1'b0; |
[44] | 22 | state_reg <= 2'd0; |
[84] | 23 | counter_reg <= 5'd0; |
[44] | 24 | end |
25 | else | |
26 | begin | |
[84] | 27 | flag_reg <= flag_next; |
[44] | 28 | state_reg <= state_next; |
29 | counter_reg <= counter_next; | |
30 | end | |
31 | end | |
32 | ||
33 | always @* | |
34 | begin | |
[84] | 35 | flag_next = flag_reg; |
[44] | 36 | state_next = state_reg; |
37 | counter_next = counter_reg; | |
38 | case (state_reg) | |
39 | 0: // skip first 16 samples | |
40 | begin | |
[84] | 41 | flag_next = 1'b0; |
[44] | 42 | if (data_ready) |
43 | begin | |
[84] | 44 | counter_next = counter_reg + 5'd1; |
[76] | 45 | if (counter_max) |
[44] | 46 | begin |
[45] | 47 | state_next = 2'd1; |
[44] | 48 | end |
49 | end | |
50 | end | |
51 | ||
52 | 1: // skip first 16 minima | |
53 | begin | |
[84] | 54 | flag_next = 1'b0; |
[44] | 55 | if (data_ready & uwt_flag[1]) |
56 | begin | |
[84] | 57 | counter_next = counter_reg + 5'd1; |
[76] | 58 | if (counter_max) |
[44] | 59 | begin |
[45] | 60 | state_next = 2'd2; |
[44] | 61 | end |
62 | end | |
63 | end | |
64 | ||
[76] | 65 | 2: |
[44] | 66 | begin |
[84] | 67 | flag_next = 1'b1; |
68 | if (data_ready) | |
[44] | 69 | begin |
[76] | 70 | if (~counter_max) |
71 | begin | |
[84] | 72 | counter_next = counter_reg + 5'd1; |
[76] | 73 | end |
[84] | 74 | if (peak_ready_int) |
75 | begin | |
76 | counter_next = 5'd0; | |
77 | end | |
78 | end | |
[44] | 79 | end |
80 | ||
81 | default: | |
82 | begin | |
[84] | 83 | flag_next = 1'b0; |
[76] | 84 | state_next = 2'd0; |
[84] | 85 | counter_next = 5'd0; |
[44] | 86 | end |
87 | endcase | |
88 | end | |
89 | ||
[84] | 90 | assign peak_ready = peak_ready_int; |
[89] | 91 | |
[44] | 92 | endmodule |
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