source: trunk/MultiChannelUSB/adc_lvds.v@ 201

Last change on this file since 201 was 159, checked in by demin, 13 years ago

adapt to paella v2

File size: 3.1 KB
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1
2(* ALTERA_ATTRIBUTE = {"{-to int_data_p} DDIO_INPUT_REGISTER=HIGH; {-to int_data_n} DDIO_INPUT_REGISTER=LOW"} *)
3
4module adc_lvds
5 #(
6 parameter size = 3, // number of channels
7 parameter width = 12 // channel resolution
8 )
9 (
10 input wire clock,
11
12 input wire lvds_dco,
13 input wire lvds_fco,
14 input wire [size-1:0] lvds_d,
15
16 input wire [1:0] trig,
17
18 output wire adc_frame,
19 output wire [size*width-1+2:0] adc_data
20
21 );
22 localparam width2 = width + 2;
23
24
25 reg state, int_rdreq, adc_frame_reg;
26 wire int_wrfull, int_rdempty;
27
28 reg [size-1:0] int_data_p, int_data_n;
29
30 reg [2:0] int_edge_reg;
31
32 reg [size*width-1:0] int_fifo_reg;
33 wire [size*width-1:0] int_fifo_wire;
34
35 reg [size*width2-1:0] int_data_reg;
36 wire [size*width2-1:0] int_data_wire;
37
38 wire [size*width-1+2:0] int_q_wire;
39 reg [size*width-1+2:0] adc_data_reg;
40
41
42
43 genvar j;
44
45 generate
46 for (j = 0; j < size; j = j + 1)
47 begin : INT_DATA
48// MSB first
49// assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_p[j], int_data_n[j]};
50// LSB first
51// assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]};
52
53 assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_reg[j*width2+width2-3:j*width2], int_data_p[j], int_data_n[j]};
54 assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-1:j*width2+2];
55// assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]};
56// assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-3:j*width2];
57 end
58 endgenerate
59
60
61 dcfifo #(
62 .intended_device_family("Cyclone III"),
63 .lpm_numwords(16),
64 .lpm_showahead("ON"),
65 .lpm_type("dcfifo"),
66 .lpm_width(size*width+2),
67 .lpm_widthu(4),
68 .rdsync_delaypipe(4),
69 .wrsync_delaypipe(4),
70 .overflow_checking("ON"),
71 .underflow_checking("ON"),
72 .use_eab("ON")) fifo_unit (
73// .data(int_data_wire),
74 .data({trig, int_fifo_reg}),
75 .rdclk(clock),
76 .rdreq((~int_rdempty) & int_rdreq),
77 .wrclk(lvds_fco),
78 .wrreq(~int_wrfull),
79 .q(int_q_wire),
80 .rdempty(int_rdempty),
81 .wrfull(int_wrfull),
82 .aclr(),
83 .rdfull(),
84 .rdusedw(),
85 .wrempty(),
86 .wrusedw());
87
88 always @ (posedge clock)
89 begin
90 case (state)
91 1'b0:
92 begin
93 int_rdreq <= 1'b1;
94 adc_frame_reg <= 1'b0;
95 state <= 1'b1;
96 end
97
98 1'b1:
99 begin
100 if (~int_rdempty)
101 begin
102 int_rdreq <= 1'b0;
103 adc_frame_reg <= 1'b1;
104 adc_data_reg <= int_q_wire;
105 state <= 1'b0;
106 end
107 end
108 endcase
109 end
110
111 always @ (negedge lvds_dco)
112 begin
113 int_data_n <= lvds_d;
114 end
115
116 always @ (posedge lvds_dco)
117 begin
118 int_data_p <= lvds_d;
119 int_data_reg <= int_data_wire;
120 int_edge_reg <= {(~int_edge_reg[1]), int_edge_reg[0], lvds_fco};
121 if (int_edge_reg[1] & int_edge_reg[2])
122 begin
123 int_fifo_reg <= int_fifo_wire;
124 end
125 end
126
127 assign adc_frame = adc_frame_reg;
128 assign adc_data = adc_data_reg;
129
130endmodule
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