Last change
on this file since 96 was 72, checked in by demin, 15 years ago |
testing all components together
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File size:
1.4 KB
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[41] | 1 | module adc_lvds
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[63] | 2 | #(
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| 3 | parameter size = 3, // number of channels
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| 4 | parameter width = 12 // channel resolution
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| 5 | )
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[41] | 6 | (
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[63] | 7 | input wire lvds_dco,
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| 8 | input wire lvds_fco,
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[72] | 9 | input wire [size-1:0] lvds_d,
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[41] | 10 |
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[63] | 11 | output wire [size*width-1:0] adc_data
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[41] | 12 | );
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| 13 |
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[63] | 14 | wire [size-1:0] int_data_h, int_data_l;
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| 15 | reg [width-1:0] int_data_next [size-1:0];
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| 16 | reg [width-1:0] int_data_reg [size-1:0];
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[41] | 17 |
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[63] | 18 | reg [width-1:0] int_adc_data [size-1:0];
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| 19 |
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| 20 | integer i;
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| 21 | genvar j;
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| 22 |
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[41] | 23 | altddio_in #(
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| 24 | .intended_device_family("Cyclone III"),
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[42] | 25 | .invert_input_clocks("ON"),
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[41] | 26 | .lpm_type("altddio_in"),
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[63] | 27 | .width(size)) altddio_in_unit (
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[41] | 28 | .datain(lvds_d),
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| 29 | .inclock(lvds_dco),
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| 30 | .aclr(1'b0),
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| 31 | .dataout_h(int_data_h),
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| 32 | .dataout_l(int_data_l),
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| 33 | .aset(1'b0),
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| 34 | .inclocken(1'b1),
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| 35 | .sclr(1'b0),
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| 36 | .sset(1'b0));
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| 37 |
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| 38 | always @ (posedge lvds_dco)
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| 39 | begin
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[63] | 40 | for (i = 0; i < size; i = i + 1)
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| 41 | begin
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| 42 | int_data_reg[i] <= int_data_next[i];
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| 43 | end
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[42] | 44 | end
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[41] | 45 |
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[42] | 46 | always @ (posedge lvds_fco)
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| 47 | begin
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[63] | 48 | for (i = 0; i < size; i = i + 1)
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| 49 | begin
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| 50 | int_adc_data[i] <= int_data_next[i];
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| 51 | end
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[41] | 52 | end
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| 53 |
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[42] | 54 | always @*
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| 55 | begin
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[63] | 56 | for (i = 0; i < size; i = i + 1)
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| 57 | begin
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| 58 | int_data_next[i] = {int_data_reg[i][9:0], int_data_l[i], int_data_h[i]};
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| 59 | end
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[42] | 60 | end
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[41] | 61 |
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[63] | 62 | generate
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[72] | 63 | for (j = 0; j < size; j = j + 1)
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[63] | 64 | begin : ADC_LVDS_OUTPUT
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| 65 | assign adc_data[j*width+width-1:j*width] = int_adc_data[j];
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| 66 | end
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| 67 | endgenerate
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| 68 |
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[58] | 69 | endmodule
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