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[41] | 1 | module adc_lvds
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| 2 | (
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| 3 | input wire lvds_dco,
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| 4 | input wire lvds_fco,
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| 5 | input wire [2:0] lvds_d,
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| 6 |
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[42] | 7 | output reg [11:0] adc_db,
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| 8 | output reg [11:0] adc_dc,
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| 9 | output reg [11:0] adc_dd
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[41] | 10 | );
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| 11 |
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| 12 |
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| 13 | wire [2:0] int_data_h, int_data_l;
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[42] | 14 | reg [11:0] int_data_next [2:0];
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[41] | 15 | reg [11:0] int_data [2:0];
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| 16 |
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| 17 | altddio_in #(
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| 18 | .intended_device_family("Cyclone III"),
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[42] | 19 | .invert_input_clocks("ON"),
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[41] | 20 | .lpm_type("altddio_in"),
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| 21 | .width(3)) altddio_in_unit (
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| 22 | .datain(lvds_d),
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| 23 | .inclock(lvds_dco),
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| 24 | .aclr(1'b0),
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| 25 | .dataout_h(int_data_h),
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| 26 | .dataout_l(int_data_l),
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| 27 | .aset(1'b0),
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| 28 | .inclocken(1'b1),
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| 29 | .sclr(1'b0),
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| 30 | .sset(1'b0));
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| 31 |
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| 32 | always @ (posedge lvds_dco)
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| 33 | begin
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[42] | 34 | int_data[0] <= int_data_next[0];
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| 35 | int_data[1] <= int_data_next[1];
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| 36 | int_data[2] <= int_data_next[2];
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| 37 | end
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[41] | 38 |
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[42] | 39 | always @ (posedge lvds_fco)
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| 40 | begin
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| 41 | adc_db <= int_data_next[0];
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| 42 | adc_dc <= int_data_next[1];
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| 43 | adc_dd <= int_data_next[2];
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[41] | 44 | end
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| 45 |
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[42] | 46 | always @*
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| 47 | begin
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| 48 | int_data_next[0] = {int_data[0][9:0], int_data_l[0], int_data_h[0]};
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| 49 | int_data_next[1] = {int_data[1][9:0], int_data_l[1], int_data_h[1]};
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| 50 | int_data_next[2] = {int_data[2][9:0], int_data_l[2], int_data_h[2]};
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| 51 | end
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[41] | 52 |
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| 53 | endmodule
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