source: trunk/MultiChannelUSB/adc_fifo.v@ 55

Last change on this file since 55 was 53, checked in by demin, 15 years ago

add signal invertor
File size: 2.9 KB
Line 
1module adc_fifo
2 (
3 input wire adc_clk,
4 input wire [11:0] adc_data,
5
6 input wire aclr,
7 input wire rdclk,
8
9 output wire ready,
10 output wire [11:0] raw_data,
11 output wire [13:0] uwt_data
12 );
13
14 wire [31:0] uwt_d1, uwt_a1, uwt_peak1;
15 wire [31:0] uwt_d2, uwt_a2, uwt_peak2;
16 wire [31:0] uwt_d3, uwt_a3, uwt_peak3;
17 wire [1:0] uwt_flag1, uwt_flag2, uwt_flag3;
18
19 wire [11:0] int_raw_q;
20 wire [13:0] int_uwt_q;
21
22 reg [11:0] int_raw_data;
23 reg [13:0] int_uwt_data;
24
25 wire [1:0] wrfull;
26
27 reg state;
28 reg int_rdreq, int_ready;
29 wire int_rdempty;
30
31 wire [11:0] int_adc_data;
32 assign int_adc_data = 12'hfff - adc_data;
33
34 uwt_bior31 #(.L(1)) uwt_1_unit (
35 .clk(adc_clk),
36 .x({20'h00000, int_adc_data}),
37 .d(uwt_d1),
38 .a(uwt_a1),
39 .peak(uwt_peak1),
40 .flag(uwt_flag1));
41
42 uwt_bior31 #(.L(2)) uwt_2_unit (
43 .clk(adc_clk),
44 .x(uwt_a1),
45 .d(uwt_d2),
46 .a(uwt_a2),
47 .peak(uwt_peak2),
48 .flag(uwt_flag2));
49
50 uwt_bior31 #(.L(3)) uwt_3_unit (
51 .clk(adc_clk),
52 .x(uwt_a2),
53 .d(uwt_d3),
54 .a(uwt_a3),
55 .peak(uwt_peak3),
56 .flag(uwt_flag3));
57
58 dcfifo #(
59 .intended_device_family("Cyclone III"),
60 .lpm_numwords(16),
61 .lpm_showahead("ON"),
62 .lpm_type("dcfifo"),
63 .lpm_width(12),
64 .lpm_widthu(4),
65 .rdsync_delaypipe(4),
66 .wrsync_delaypipe(4),
67 .overflow_checking("ON"),
68 .underflow_checking("ON"),
69 .use_eab("OFF"),
70 .write_aclr_synch("OFF")) fifo_raw (
71 .aclr(aclr),
72 .data(int_adc_data),
73 .rdclk(rdclk),
74 .rdreq((~int_rdempty) & int_rdreq),
75 .wrclk(adc_clk),
76 .wrreq(~wrfull[0]),
77 .q(int_raw_q),
78 .rdempty(int_rdempty),
79 .wrfull(wrfull[0]),
80 .rdfull(),
81 .rdusedw(),
82 .wrempty(),
83 .wrusedw());
84
85 dcfifo #(
86 .intended_device_family("Cyclone III"),
87 .lpm_numwords(16),
88 .lpm_showahead("ON"),
89 .lpm_type("dcfifo"),
90 .lpm_width(14),
91 .lpm_widthu(4),
92 .rdsync_delaypipe(4),
93 .wrsync_delaypipe(4),
94 .overflow_checking("ON"),
95 .underflow_checking("ON"),
96 .use_eab("OFF"),
97 .write_aclr_synch("OFF")) fifo_uwt (
98 .aclr(aclr),
99 .data({uwt_flag3, uwt_peak3[11:0]}),
100 .rdclk(rdclk),
101 .rdreq((~int_rdempty) & int_rdreq),
102 .wrclk(adc_clk),
103 .wrreq(~wrfull[1]),
104 .q(int_uwt_q),
105 .rdempty(),
106 .wrfull(wrfull[1]),
107 .rdfull(),
108 .rdusedw(),
109 .wrempty(),
110 .wrusedw());
111
112 always @ (posedge rdclk)
113 begin
114 case (state)
115 1'b0:
116 begin
117 int_rdreq <= 1'b1;
118 int_ready <= 1'b0;
119 state <= 1'b1;
120 end
121
122 1'b1:
123 begin
124 if (~int_rdempty)
125 begin
126 int_raw_data <= int_raw_q;
127 int_uwt_data <= int_uwt_q;
128 int_rdreq <= 1'b0;
129 int_ready <= 1'b1;
130 state <= 1'b0;
131 end
132 end
133
134 default:
135 begin
136 int_rdreq <= 1'b1;
137 int_ready <= 1'b0;
138 state <= 1'b1;
139 end
140 endcase
141 end
142
143 assign ready = int_ready;
144 assign raw_data = int_raw_data;
145 assign uwt_data = int_uwt_data;
146
147endmodule
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