source: trunk/MultiChannelUSB/adc_fifo.v@ 49

Last change on this file since 49 was 49, checked in by demin, 15 years ago

add registers for output data
File size: 2.8 KB
RevLine 
[27]1module adc_fifo
2 (
3 input wire adc_clk,
4 input wire [11:0] adc_data,
5
6 input wire aclr,
7 input wire rdclk,
[44]8
9 output wire ready,
[27]10 output wire [11:0] raw_data,
11 output wire [13:0] uwt_data
12 );
13
14 wire [31:0] uwt_d1, uwt_a1, uwt_peak1;
15 wire [31:0] uwt_d2, uwt_a2, uwt_peak2;
16 wire [31:0] uwt_d3, uwt_a3, uwt_peak3;
17 wire [1:0] uwt_flag1, uwt_flag2, uwt_flag3;
18
[49]19 wire [11:0] int_raw_q;
20 wire [13:0] int_uwt_q;
21
22 reg [11:0] int_raw_data;
23 reg [13:0] int_uwt_data;
24
[27]25 wire [1:0] wrfull;
[44]26
27 reg state;
28 reg int_rdreq, int_ready;
29 wire int_rdempty;
[27]30
31 uwt_bior31 #(.L(1)) uwt_1_unit (
32 .clk(adc_clk),
[44]33 .x({20'h00000, adc_data}),
[27]34 .d(uwt_d1),
35 .a(uwt_a1),
36 .peak(uwt_peak1),
37 .flag(uwt_flag1));
38
39 uwt_bior31 #(.L(2)) uwt_2_unit (
40 .clk(adc_clk),
41 .x(uwt_a1),
42 .d(uwt_d2),
43 .a(uwt_a2),
44 .peak(uwt_peak2),
45 .flag(uwt_flag2));
46
47 uwt_bior31 #(.L(3)) uwt_3_unit (
48 .clk(adc_clk),
49 .x(uwt_a2),
50 .d(uwt_d3),
51 .a(uwt_a3),
52 .peak(uwt_peak3),
53 .flag(uwt_flag3));
54
[45]55 dcfifo #(
56 .intended_device_family("Cyclone III"),
57 .lpm_numwords(16),
58 .lpm_showahead("ON"),
59 .lpm_type("dcfifo"),
60 .lpm_width(12),
61 .lpm_widthu(4),
62 .rdsync_delaypipe(4),
63 .wrsync_delaypipe(4),
64 .overflow_checking("ON"),
65 .underflow_checking("ON"),
66 .use_eab("OFF"),
67 .write_aclr_synch("OFF")) fifo_raw (
[27]68 .aclr(aclr),
69 .data(adc_data),
70 .rdclk(rdclk),
[49]71 .rdreq((~int_rdempty) & int_rdreq),
[27]72 .wrclk(adc_clk),
73 .wrreq(~wrfull[0]),
[49]74 .q(int_raw_q),
[44]75 .rdempty(int_rdempty),
[45]76 .wrfull(wrfull[0]),
77 .rdfull(),
78 .rdusedw(),
79 .wrempty(),
80 .wrusedw());
[27]81
[45]82 dcfifo #(
83 .intended_device_family("Cyclone III"),
84 .lpm_numwords(16),
85 .lpm_showahead("ON"),
86 .lpm_type("dcfifo"),
87 .lpm_width(14),
88 .lpm_widthu(4),
89 .rdsync_delaypipe(4),
90 .wrsync_delaypipe(4),
91 .overflow_checking("ON"),
92 .underflow_checking("ON"),
93 .use_eab("OFF"),
94 .write_aclr_synch("OFF")) fifo_uwt (
[27]95 .aclr(aclr),
96 .data({uwt_flag3, uwt_peak3[11:0]}),
97 .rdclk(rdclk),
[49]98 .rdreq((~int_rdempty) & int_rdreq),
[27]99 .wrclk(adc_clk),
100 .wrreq(~wrfull[1]),
[49]101 .q(int_uwt_q),
[27]102 .rdempty(),
[45]103 .wrfull(wrfull[1]),
104 .rdfull(),
105 .rdusedw(),
106 .wrempty(),
107 .wrusedw());
[27]108
[44]109 always @ (posedge rdclk)
110 begin
111 case (state)
112 1'b0:
113 begin
[49]114 int_rdreq <= 1'b1;
115 int_ready <= 1'b0;
116 state <= 1'b1;
117 end
118
119 1'b1:
120 begin
[44]121 if (~int_rdempty)
122 begin
[49]123 int_raw_data <= int_raw_q;
124 int_uwt_data <= int_uwt_q;
125 int_rdreq <= 1'b0;
[44]126 int_ready <= 1'b1;
[49]127 state <= 1'b0;
[44]128 end
129 end
130
131 default:
132 begin
[49]133 int_rdreq <= 1'b1;
[44]134 int_ready <= 1'b0;
[49]135 state <= 1'b1;
[44]136 end
137 endcase
138 end
139
140 assign ready = int_ready;
[49]141 assign raw_data = int_raw_data;
142 assign uwt_data = int_uwt_data;
[44]143
[27]144endmodule
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