source: trunk/MultiChannelUSB/Paella.v@ 98

Last change on this file since 98 was 90, checked in by demin, 15 years ago

full rewrite

File size: 9.5 KB
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1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire I2C_SDA,
8 inout wire I2C_SCL,
9 inout wire [4:0] CON_A,
10 input wire [15:0] CON_B,
11 input wire [12:0] CON_C,
12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
17 input wire [2:0] ADC_D,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 localparam N = 3;
46
47 // Turn output ports off
48/*
49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
53*/
54 assign RAM_CLK = sys_clock;
55 assign RAM_CE1 = 1'b0;
56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
59 assign CON_A = 5'bz;
60 assign USB_PA0 = 1'bz;
61 assign USB_PA1 = 1'bz;
62 assign USB_PA3 = 1'bz;
63 assign USB_PA7 = 1'bz;
64// assign RAM_DQAP = 1'bz;
65// assign RAM_DQA = 8'bz;
66// assign RAM_DQBP = 1'bz;
67// assign RAM_DQB = 8'bz;
68
69 assign USB_PA2 = ~usb_rden;
70 assign USB_PA4 = usb_addr[0];
71 assign USB_PA5 = usb_addr[1];
72 assign USB_PA6 = ~usb_pktend;
73
74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
75 wire usb_tx_wrreq, usb_rx_rdreq;
76 wire usb_tx_full, usb_rx_empty;
77 wire [7:0] usb_tx_data, usb_rx_data;
78 wire [1:0] usb_addr;
79
80 assign USB_SLRD = ~usb_rdreq;
81 assign USB_SLWR = ~usb_wrreq;
82
83 usb_fifo usb_unit
84 (
85 .usb_clk(USB_IFCLK),
86 .usb_data(USB_PB),
87 .usb_full(~USB_FLAGB),
88 .usb_empty(~USB_FLAGA),
89 .usb_wrreq(usb_wrreq),
90 .usb_rdreq(usb_rdreq),
91 .usb_rden(usb_rden),
92 .usb_pktend(usb_pktend),
93 .usb_addr(usb_addr),
94
95 .clk(sys_clock),
96
97 .tx_full(usb_tx_full),
98 .tx_wrreq(usb_tx_wrreq),
99 .tx_data(usb_tx_data),
100
101 .rx_empty(usb_rx_empty),
102 .rx_rdreq(usb_rx_rdreq),
103 .rx_q(usb_rx_data)
104 );
105
106 wire ana_good [N-1:0];
107 wire [11:0] ana_data [N-1:0];
108 wire [11:0] ana_base [N-1:0];
109
110 wire [11:0] osc_mux_data [N-1:0];
111
112 wire [11:0] trg_mux_data;
113 wire trg_flag;
114
115 wire [83:0] int_mux_data [N-1:0];
116
117 wire sys_clock, sys_frame;
118
119 wire [11:0] adc_data [N-1:0];
120 wire [11:0] int_data [N-1:0];
121 wire [11:0] cmp_data;
122 wire [11:0] nowhere;
123
124 wire [31:0] uwt_d1 [N-1:0];
125 wire [31:0] uwt_a1 [N-1:0];
126 wire [31:0] uwt_peak1 [N-1:0];
127 wire [31:0] uwt_d2 [N-1:0];
128 wire [31:0] uwt_a2 [N-1:0];
129 wire [31:0] uwt_peak2 [N-1:0];
130 wire [31:0] uwt_d3 [N-1:0];
131 wire [31:0] uwt_a3 [N-1:0];
132 wire [31:0] uwt_peak3 [N-1:0];
133
134 wire [1:0] uwt_flag1 [N-1:0];
135 wire [1:0] uwt_flag2 [N-1:0];
136 wire [1:0] uwt_flag3 [N-1:0];
137
138 wire i2c_reset;
139
140/*
141 adc_para adc_para_unit (
142 .lvds_dco(ADC_DCO),
143 .lvds_fco(ADC_FCO),
144 .para_good(CON_CCLK[0]),
145 .para_data(CON_C[11:0]),
146 .adc_data(adc_data[2]));
147*/
148/*
149 wire adc_pll_clk;
150
151 adc_pll adc_pll_unit(
152 .inclk0(ADC_FCO),
153 .c0(adc_pll_clk));
154*/
155
156 test test_unit(
157 .clk(ADC_FCO),
158// .data(adc_data[2]));
159 .data(nowhere));
160
161 adc_lvds #(
162 .size(3),
163 .width(12)) adc_lvds_unit (
164 .lvds_dco(ADC_DCO),
165// .lvds_dco(adc_pll_clk),
166 .lvds_fco(ADC_FCO),
167 .lvds_d(ADC_D[2:0]),
168 .adc_data({ adc_data[2],
169// .adc_data({ nowhere,
170 adc_data[1],
171 adc_data[0] }));
172
173 assign cmp_data = CON_B[11:0];
174 assign sys_clock = ADC_DCO;
175 assign sys_frame = ADC_FCO;
176
177 wire [15:0] cfg_bits [15:0];
178 wire [255:0] int_cfg_bits;
179
180 wire [31:0] cfg_mux_selector;
181
182 wire cfg_reset;
183
184 wire [7:0] bus_ssel;
185 wire bus_wren;
186 wire [31:0] bus_addr;
187 wire [15:0] bus_mosi;
188 wire [15:0] bus_miso [5:0];
189 wire [5:0] bus_busy;
190
191 wire [15:0] mrg_bus_miso;
192 wire mrg_bus_busy;
193
194 wire [79:0] int_bus_miso;
195
196 genvar j;
197
198 generate
199 for (j = 0; j < 16; j = j + 1)
200 begin : CONFIGURATION_OUTPUT
201 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
202 end
203 endgenerate
204
205 configuration configuration_unit (
206 .clock(sys_clock),
207 .reset(cfg_reset),
208 .bus_ssel(bus_ssel[0]),
209 .bus_wren(bus_wren),
210 .bus_addr(bus_addr[3:0]),
211 .bus_mosi(bus_mosi),
212 .bus_miso(bus_miso[0]),
213 .bus_busy(bus_busy[0]),
214 .cfg_bits(int_cfg_bits));
215
216 generate
217 for (j = 0; j < 3; j = j + 1)
218 begin : MUX_DATA
219 assign int_mux_data[j] = {
220 {ana_good[j], 11'd0},
221 ana_data[j],
222 ana_base[j],
223 uwt_a3[j][20:9],
224 uwt_a2[j][17:6],
225 uwt_a1[j][14:3],
226 adc_data[j]};
227 end
228 endgenerate
229
230 assign cfg_mux_selector = {cfg_bits[11], cfg_bits[10]};
231
232 lpm_mux #(
233 .lpm_size(21),
234 .lpm_type("LPM_MUX"),
235 .lpm_width(12),
236 .lpm_widths(5)) trg_mux_unit (
237 .sel(cfg_mux_selector[28:24]),
238 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
239 .result(trg_mux_data));
240
241 generate
242 for (j = 0; j < 3; j = j + 1)
243 begin : OSC_CHAIN
244
245 lpm_mux #(
246 .lpm_size(21),
247 .lpm_type("LPM_MUX"),
248 .lpm_width(12),
249 .lpm_widths(5)) osc_mux_unit (
250 .sel(cfg_mux_selector[j*8+4:j*8]),
251 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
252 .result(osc_mux_data[j]));
253
254 end
255 endgenerate
256
257 trigger trigger_unit (
258 .clock(sys_clock),
259 .frame(sys_frame),
260 .reset(cfg_bits[12][14]),
261 .cfg_data(cfg_bits[12][11:0]),
262 .trg_data(trg_mux_data),
263 .trg_flag(trg_flag));
264
265 oscilloscope oscilloscope_unit (
266 .clock(sys_clock),
267 .frame(sys_frame),
268 .reset(cfg_bits[12][13]),
269 .cfg_data({cfg_bits[12][12], cfg_bits[13]}),
270 .trg_flag(trg_flag),
271 .osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
272 .ram_wren(RAM_WE),
273 .ram_addr(RAM_ADDR),
274 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
275 .bus_ssel(bus_ssel[1]),
276 .bus_wren(bus_wren),
277 .bus_addr(bus_addr[19:0]),
278 .bus_mosi(bus_mosi),
279 .bus_miso(bus_miso[1]),
280 .bus_busy(bus_busy[1]));
281
282 generate
283 for (j = 0; j < 3; j = j + 1)
284 begin : MCA_CHAIN
285
286 assign int_data[j] = (cfg_bits[0][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
287
288 uwt_bior31 #(.L(1)) uwt_1_unit (
289 .clock(sys_clock),
290 .frame(sys_frame),
291 .reset(1'b0),
292 .x({20'h00000, int_data[j]}),
293 .d(uwt_d1[j]),
294 .a(uwt_a1[j]),
295 .peak(uwt_peak1[j]),
296 .flag(uwt_flag1[j]));
297
298 uwt_bior31 #(.L(2)) uwt_2_unit (
299 .clock(sys_clock),
300 .frame(sys_frame),
301 .reset(1'b0),
302 .x(uwt_a1[j]),
303 .d(uwt_d2[j]),
304 .a(uwt_a2[j]),
305 .peak(uwt_peak2[j]),
306 .flag(uwt_flag2[j]));
307
308 uwt_bior31 #(.L(3)) uwt_3_unit (
309 .clock(sys_clock),
310 .frame(sys_frame),
311 .reset(1'b0),
312 .x(uwt_a2[j]),
313 .d(uwt_d3[j]),
314 .a(uwt_a3[j]),
315 .peak(uwt_peak3[j]),
316 .flag(uwt_flag3[j]));
317
318 analyser analyser_unit (
319 .clock(sys_clock),
320 .frame(sys_frame),
321 .reset(cfg_bits[2+2*j][12]),
322 .cfg_data({cfg_bits[2+2*j][11:0], cfg_bits[1+2*j][12:0]}),
323 .uwt_flag(uwt_flag3[j]),
324 .uwt_data(uwt_peak3[j]),
325 .ana_good(ana_good[j]),
326 .ana_data(ana_data[j]),
327 .ana_base(ana_base[j]));
328
329 histogram histogram_unit (
330 .clock(sys_clock),
331 .frame(sys_frame),
332 .reset(cfg_bits[7+j][13]),
333 .cfg_data(cfg_bits[7+j][12:0]),
334 .hst_good(ana_good[j]),
335 .hst_data(ana_data[j]),
336 .bus_ssel(bus_ssel[2+j]),
337 .bus_wren(bus_wren),
338 .bus_addr(bus_addr[12:0]),
339 .bus_mosi(bus_mosi),
340 .bus_miso(bus_miso[2+j]),
341 .bus_busy(bus_busy[2+j]));
342
343 end
344 endgenerate
345
346 i2c_fifo i2c_unit(
347 .clock(sys_clock),
348 .reset(i2c_reset),
349/*
350 normal connection
351 .i2c_sda(I2C_SDA),
352 .i2c_scl(I2C_SCL),
353
354 following is a cross wire connection for EPT
355*/
356 .i2c_sda(I2C_SCL),
357 .i2c_scl(I2C_SDA),
358
359 .bus_ssel(bus_ssel[5]),
360 .bus_wren(bus_wren),
361 .bus_mosi(bus_mosi),
362 .bus_busy(bus_busy[5]));
363
364 generate
365 for (j = 0; j < 5; j = j + 1)
366 begin : BUS_OUTPUT
367 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
368 end
369 endgenerate
370
371 lpm_mux #(
372 .lpm_size(5),
373 .lpm_type("LPM_MUX"),
374 .lpm_width(16),
375 .lpm_widths(3)) bus_miso_mux_unit (
376 .sel(bus_addr[30:28]),
377 .data(int_bus_miso),
378 .result(mrg_bus_miso));
379
380 lpm_mux #(
381 .lpm_size(6),
382 .lpm_type("LPM_MUX"),
383 .lpm_width(1),
384 .lpm_widths(3)) bus_busy_mux_unit (
385 .sel(bus_addr[30:28]),
386 .data(bus_busy),
387 .result(mrg_bus_busy));
388
389/*
390 lpm_or #(
391 .lpm_size(6),
392 .lpm_type("LPM_OR"),
393 .lpm_width(16)) bus_miso_or_unit (
394 .data(int_bus_miso),
395 .result(mrg_bus_miso));
396*/
397
398 lpm_decode #(
399 .lpm_decodes(8),
400 .lpm_type("LPM_DECODE"),
401 .lpm_width(3)) lpm_decode_unit (
402 .data(bus_addr[30:28]),
403 .eq(bus_ssel),
404 .aclr(),
405 .clken(),
406 .clock(),
407 .enable());
408
409 control control_unit (
410 .clock(sys_clock),
411 .rx_empty(usb_rx_empty),
412 .tx_full(usb_tx_full),
413 .rx_data(usb_rx_data),
414 .rx_rdreq(usb_rx_rdreq),
415 .tx_wrreq(usb_tx_wrreq),
416 .tx_data(usb_tx_data),
417 .bus_wren(bus_wren),
418 .bus_addr(bus_addr),
419 .bus_mosi(bus_mosi),
420 .bus_miso(mrg_bus_miso),
421 .bus_busy(mrg_bus_busy),
422 .led(LED));
423
424/*
425 altserial_flash_loader #(
426 .enable_shared_access("OFF"),
427 .enhanced_mode(1),
428 .intended_device_family("Cyclone III")) sfl_unit (
429 .noe(1'b0),
430 .asmi_access_granted(),
431 .asmi_access_request(),
432 .data0out(),
433 .dclkin(),
434 .scein(),
435 .sdoin());
436*/
437
438endmodule
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