source: trunk/MultiChannelUSB/Paella.v@ 43

Last change on this file since 43 was 42, checked in by demin, 15 years ago

code cleanup
File size: 8.9 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire [2:0] ADC_D,
16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 input wire USB_FLAGC,
23 inout wire USB_PA0,
24 inout wire USB_PA1,
25 output wire USB_PA2,
26 inout wire USB_PA3,
27 output wire USB_PA4,
28 output wire USB_PA5,
29 output wire USB_PA6,
30 inout wire USB_PA7,
31 inout wire [7:0] USB_PB,
32
33 output wire RAM_CLK,
34 output wire RAM_CE1,
35 output wire RAM_WE,
36 output wire [19:0] RAM_ADDR,
37 inout wire RAM_DQAP,
38 inout wire [7:0] RAM_DQA,
39 inout wire RAM_DQBP,
40 inout wire [7:0] RAM_DQB
41 );
42
43 // Turn output ports off
44 assign RAM_CLK = 1'b0;
45 assign RAM_CE1 = 1'b0;
46 assign RAM_WE = 1'b0;
47 assign RAM_ADDR = 20'h00000;
48
49 // Turn inout ports to tri-state
50 assign TRG = 4'bz;
51 assign CON_A = 7'bz;
52 assign CON_B = 16'bz;
53 assign CON_C = 13'bz;
54 assign USB_PA0 = 1'bz;
55 assign USB_PA1 = 1'bz;
56 assign USB_PA3 = 1'bz;
57 assign USB_PA7 = 1'bz;
58 assign RAM_DQAP = 1'bz;
59 assign RAM_DQA = 8'bz;
60 assign RAM_DQBP = 1'bz;
61 assign RAM_DQB = 8'bz;
62
63
64 assign USB_PA2 = ~usb_rden;
65 assign USB_PA4 = usb_addr[0];
66 assign USB_PA5 = usb_addr[1];
67 assign USB_PA6 = ~usb_pktend;
68
69 reg [31:0] counter;
70 reg led_reg;
71// assign LED = counter[24];
72 assign LED = led_reg;
73
74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
75 wire usb_fifo_aclr;
76 reg usb_fifo_tx_wrreq;
77 reg usb_fifo_rx_rdreq;
78 wire usb_fifo_tx_full, usb_fifo_rx_empty;
79 reg [7:0] usb_fifo_tx_data;
80 wire [7:0] usb_fifo_rx_data;
81 wire [1:0] usb_addr;
82
83 assign USB_SLRD = ~usb_rdreq;
84 assign USB_SLWR = ~usb_wrreq;
85
86 usb_fifo usb_fifo_unit
87 (
88 .usb_clk(USB_IFCLK),
89 .usb_data(USB_PB),
90 .usb_full(~USB_FLAGB),
91 .usb_empty(~USB_FLAGA),
92 .usb_wrreq(usb_wrreq),
93 .usb_rdreq(usb_rdreq),
94 .usb_rden(usb_rden),
95 .usb_pktend(usb_pktend),
96 .usb_addr(usb_addr),
97
98 .clk(CLK_50MHz),
99 .aclr(usb_fifo_aclr),
100
101 .tx_full(usb_fifo_tx_full),
102 .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
103 .tx_data(usb_fifo_tx_data),
104
105 .rx_empty(usb_fifo_rx_empty),
106 .rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
107 .rx_q(usb_fifo_rx_data)
108 );
109
110 reg [23:0] rx_counter;
111 reg [10:0] tst_counter;
112
113 reg [9:0] osc_counter;
114 reg osc_reset;
115 reg osc_byte_num;
116 wire [9:0] osc_start_addr;
117 reg [9:0] osc_addr;
118 wire [15:0] osc_q;
119
120 reg hst_reset;
121 reg [1:0] hst_byte_num;
122 reg [11:0] hst_addr;
123 wire [31:0] hst_q;
124
125 reg [3:0] state0, state1, state2;
126 reg adc_fifo_rdreq;
127 wire adc_fifo_rdempty;
128 reg adc_fifo_aclr;
129
130 reg [31:0] adc_counter;
131 reg adc_data_ready;
132 wire adc_clk;
133
134 reg [11:0] adc_data;
135
136 wire [11:0] adc_lvds_data [2:0];
137
138 wire [11:0] raw_data;
139 wire [11:0] uwt_data;
140 wire [1:0] uwt_flag;
141
142 pll pll_unit(
143 .inclk0(CLK_50MHz),
144 .c0(adc_clk));
145/*
146 altserial_flash_loader #(
147 .enable_shared_access("OFF"),
148 .enhanced_mode(1),
149 .intended_device_family("Cyclone III")) sfl_unit (
150 .noe(1'b0),
151 .asmi_access_granted(),
152 .asmi_access_request(),
153 .data0out(),
154 .dclkin(),
155 .scein(),
156 .sdoin());
157*/
158 adc_lvds adc_lvds_unit (
159 .lvds_dco(ADC_DCO),
160 .lvds_fco(ADC_FCO),
161 .lvds_d(ADC_D),
162 .adc_db(adc_lvds_data[0]),
163 .adc_dc(adc_lvds_data[1]),
164 .adc_dd(adc_lvds_data[2]));
165
166 adc_fifo adc_fifo_unit (
167 .adc_clk(ADC_FCO),
168 .adc_data(adc_lvds_data[1]),
169 .aclr(adc_fifo_aclr),
170 .rdclk(CLK_50MHz),
171 .rdreq(adc_fifo_rdreq),
172 .rdempty(adc_fifo_rdempty),
173 .raw_data(raw_data),
174 .uwt_data({uwt_flag, uwt_data}));
175
176 histogram histogram_unit (
177 .clk(CLK_50MHz),
178 .reset(hst_reset),
179 .data_ready(adc_data_ready),
180 .data(raw_data),
181 .address(hst_addr),
182 .q(hst_q));
183
184 oscilloscope oscilloscope_unit (
185 .clk(CLK_50MHz),
186 .reset(osc_reset),
187 .data_ready(adc_data_ready),
188 .raw_data(raw_data),
189 .uwt_data(uwt_data),
190 .threshold(16'd100),
191 .address(osc_addr),
192 .start_address(osc_start_addr),
193 .q(osc_q));
194
195/*
196 always @ (posedge adc_clk)
197 begin
198 counter <= counter + 32'd1;
199 end
200*/
201
202 always @ (posedge CLK_50MHz)
203 begin
204 case (state0)
205 1:
206 begin
207 if (~adc_fifo_rdempty)
208 begin
209// adc_counter <= adc_counter + 32'd1;
210 adc_fifo_rdreq <= 1'b1;
211 adc_data_ready <= 1'b1;
212 state0 <= 4'd2;
213 end
214 end
215
216 2:
217 begin
218 adc_fifo_rdreq <= 1'b0;
219 adc_data_ready <= 1'b0;
220 state0 <= 4'd1;
221 end
222
223 default:
224 begin
225 state0 <= 4'd1;
226 end
227 endcase
228 end
229
230 always @(posedge CLK_50MHz)
231 begin
232 if (~usb_fifo_rx_empty)
233 begin
234 led_reg <= 1'b0;
235 rx_counter <= 24'd0;
236 end
237 else
238 begin
239 if (&rx_counter)
240 begin
241 led_reg <= 1'b1;
242 end
243 else
244 begin
245 rx_counter <= rx_counter + 24'd1;
246 end
247 end
248
249 case(state1)
250 1:
251 begin
252 usb_fifo_rx_rdreq <= 1'b1;
253 usb_fifo_tx_wrreq <= 1'b0;
254 hst_reset <= 1'b0;
255 osc_reset <= 1'b0;
256 state1 <= 4'd2;
257 end
258
259 2:
260 begin
261 if (~usb_fifo_rx_empty)
262 begin
263 case (usb_fifo_rx_data)
264 8'h30:
265 begin
266 usb_fifo_rx_rdreq <= 1'b0;
267 hst_reset <= 1'b1;
268 state1 <= 4'd1;
269 end
270 8'h31:
271 begin
272 usb_fifo_rx_rdreq <= 1'b0;
273 hst_addr <= 12'd0;
274 hst_byte_num <= 2'd0;
275 state1 <= 4'd3;
276 end
277 8'h32:
278 begin
279 usb_fifo_rx_rdreq <= 1'b0;
280 osc_reset <= 1'b1;
281 state1 <= 4'd1;
282 end
283 8'h33:
284 begin
285 usb_fifo_rx_rdreq <= 1'b0;
286 osc_addr <= osc_start_addr;
287 osc_counter <= 10'd0;
288 osc_byte_num <= 1'd0;
289 state1 <= 4'd6;
290 end
291 8'h34:
292 begin
293 usb_fifo_rx_rdreq <= 1'b0;
294 state1 <= 4'd1;
295 end
296 8'h35:
297 begin
298 usb_fifo_rx_rdreq <= 1'b0;
299 tst_counter <= 11'd0;
300 state1 <= 4'd9;
301 end
302 endcase
303 end
304 end
305
306 // hst transfer
307 3:
308 begin
309 usb_fifo_tx_data <= hst_q[7:0];
310 usb_fifo_tx_wrreq <= 1'b1;
311 hst_byte_num <= 2'd1;
312 state1 <= 4'd4;
313 end
314 4:
315 begin
316 if (~usb_fifo_tx_full)
317 begin
318 case (hst_byte_num)
319 2'd0: usb_fifo_tx_data <= hst_q[7:0];
320 2'd1: usb_fifo_tx_data <= hst_q[15:8];
321 2'd2: usb_fifo_tx_data <= hst_q[23:16];
322 2'd3: usb_fifo_tx_data <= hst_q[31:24];
323 endcase
324 if ((&hst_byte_num) & (&hst_addr))
325 begin
326 state1 <= 4'd5;
327 end
328 else
329 begin
330 if (&hst_byte_num)
331 begin
332 hst_addr <= hst_addr + 12'd1;
333 end
334 hst_byte_num <= hst_byte_num + 2'd1;
335 end
336 end
337 end
338 5:
339 begin
340 if (~usb_fifo_tx_full)
341 begin
342 usb_fifo_tx_wrreq <= 1'b0;
343 state1 <= 4'd1;
344 end
345 end
346
347 // osc transfer
348 6:
349 begin
350 usb_fifo_tx_data <= osc_q[7:0];
351 usb_fifo_tx_wrreq <= 1'b1;
352 osc_byte_num <= 1'd1;
353 state1 <= 4'd7;
354 end
355 7:
356 begin
357 if (~usb_fifo_tx_full)
358 begin
359 case (osc_byte_num)
360 1'd0: usb_fifo_tx_data <= osc_q[7:0];
361 1'd1: usb_fifo_tx_data <= osc_q[15:8];
362 endcase
363 if ((&osc_byte_num) & (&osc_counter))
364 begin
365 state1 <= 4'd8;
366 end
367 else
368 begin
369 if (&osc_byte_num)
370 begin
371 osc_addr <= osc_addr + 10'd1;
372 osc_counter <= osc_counter + 10'd1;
373 end
374 osc_byte_num <= osc_byte_num + 1'd1;
375 end
376 end
377 end
378 8:
379 begin
380 if (~usb_fifo_tx_full)
381 begin
382 usb_fifo_tx_wrreq <= 1'b0;
383 state1 <= 4'd1;
384 end
385 end
386 // tst transfer
387 9:
388 begin
389 usb_fifo_tx_data <= tst_counter;
390 usb_fifo_tx_wrreq <= 1'b1;
391 tst_counter <= tst_counter + 11'd1;
392 state1 <= 4'd10;
393 end
394 10:
395 begin
396 if (~usb_fifo_tx_full)
397 begin
398 usb_fifo_tx_data <= tst_counter;
399 if (tst_counter == 11'd0) //(&osc_counter)
400 begin
401 state1 <= 4'd11;
402 end
403 else
404 begin
405 tst_counter <= tst_counter + 11'd1;
406 end
407 end
408 end
409 11:
410 begin
411 if (~usb_fifo_tx_full)
412 begin
413 usb_fifo_tx_wrreq <= 1'b0;
414 state1 <= 4'd1;
415 end
416 end
417
418 default:
419 begin
420 state1 <= 4'd1;
421 end
422 endcase
423 end
424
425 always @ (posedge adc_clk)
426 begin
427 case (state2)
428 1:
429 begin
430 adc_data <= 12'd0;
431 state2 <= 4'd2;
432 end
433
434 2:
435 begin
436 adc_data <= 12'd1024;
437 state2 <= 4'd3;
438 end
439
440 3:
441 begin
442 adc_data <= 12'd2048;
443 state2 <= 4'd4;
444 end
445
446 4:
447 begin
448 adc_data <= 12'd3072;
449 state2 <= 4'd5;
450 end
451
452 5:
453 begin
454 adc_data <= 12'd4095;
455 state2 <= 4'd1;
456 end
457
458 default:
459 begin
460 state2 <= 4'd1;
461 end
462 endcase
463 end
464
465endmodule
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