source: trunk/MultiChannelUSB/Paella.v@ 27

Last change on this file since 27 was 27, checked in by demin, 15 years ago

initial commit
File size: 4.4 KB
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1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire ADC_DB,
16 input wire ADC_DC,
17 input wire ADC_DD,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire [7:0] USB_PA,
26 inout wire [7:0] USB_PB,
27
28 output wire RAM_CLK,
29 output wire RAM_CE1,
30 output wire RAM_WE,
31 output wire [19:0] RAM_ADDR,
32 inout wire RAM_DQAP,
33 inout wire [7:0] RAM_DQA,
34 inout wire RAM_DQBP,
35 inout wire [7:0] RAM_DQB
36 );
37
38 // Turn output ports off
39 assign RAM_CLK = 1'b0;
40 assign RAM_CE1 = 1'b0;
41 assign RAM_WE = 1'b0;
42 assign RAM_ADDR = 20'h00000;
43
44 // Turn inout ports to tri-state
45 assign TRG = 4'bz;
46 assign CON_A = 7'bz;
47 assign CON_B = 16'bz;
48 assign CON_C = 13'bz;
49 assign USB_PA = {1'bz, ~usb_pktend, usb_addr, 1'bz, ~usb_rden, 2'bz};
50 assign RAM_DQAP = 1'bz;
51 assign RAM_DQA = 8'bz;
52 assign RAM_DQBP = 1'bz;
53 assign RAM_DQB = 8'bz;
54
55 reg [31:0] counter;
56 assign LED = counter[24];
57// assign LED = usb_fifo_led;
58
59 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
60 wire usb_fifo_aclr, usb_fifo_led;
61 wire usb_fifo_tx_wrreq, usb_fifo_rx_rdreq;
62 wire usb_fifo_tx_full, usb_fifo_rx_empty;
63 wire [7:0] usb_fifo_tx_data, usb_fifo_rx_data;
64 wire [1:0] usb_addr;
65
66 assign USB_SLRD = ~usb_rdreq;
67 assign USB_SLWR = ~usb_wrreq;
68
69 usb_fifo usb_fifo_unit
70 (
71 .usb_clk(USB_IFCLK),
72 .usb_data(USB_PB),
73 .usb_full(~USB_FLAGB),
74 .usb_empty(~USB_FLAGA),
75 .usb_wrreq(usb_wrreq),
76 .usb_rdreq(usb_rdreq),
77 .usb_rden(usb_rden),
78 .usb_pktend(usb_pktend),
79 .usb_addr(usb_addr),
80 .clk(CLK_50MHz),
81 .aclr(usb_fifo_aclr),
82 .tx_wrreq(usb_fifo_tx_wrreq),
83 .rx_rdreq(usb_fifo_rx_rdreq),
84 .tx_data(usb_fifo_tx_data),
85 .tx_full(usb_fifo_tx_full),
86 .rx_empty(usb_fifo_rx_empty),
87// .led(usb_fifo_led),
88 .rx_data(usb_fifo_rx_data)
89 );
90
91 reg [9:0] osc_counter;
92 reg osc_reset;
93 reg osc_bit_num;
94 wire [9:0] osc_start_addr;
95 reg [9:0] osc_addr;
96 wire [15:0] osc_q;
97
98 reg hst_reset;
99 reg [1:0] hst_bit_num;
100 reg [11:0] hst_addr;
101 wire [31:0] hst_q;
102
103 reg [3:0] state0, state1, state2;
104 reg adc_fifo_rdreq;
105 wire adc_fifo_rdempty;
106 reg adc_fifo_aclr;
107
108 reg [31:0] adc_counter;
109 reg adc_data_ready;
110 wire adc_clk;
111 reg [11:0] adc_data;
112 wire [11:0] raw_data;
113 wire [11:0] uwt_data;
114 wire [1:0] uwt_flag;
115
116 pll pll_unit(
117 .inclk0(CLK_50MHz),
118 .c0(adc_clk));
119
120 adc_fifo adc_fifo_unit (
121 .adc_clk(adc_clk),
122 .adc_data(adc_data),
123 .aclr(adc_fifo_aclr),
124 .rdclk(CLK_50MHz),
125 .rdreq(adc_fifo_rdreq),
126 .rdempty(adc_fifo_rdempty),
127 .raw_data(raw_data),
128 .uwt_data({uwt_flag, uwt_data}));
129
130 histogram histogram_unit (
131 .clk(CLK_50MHz),
132 .reset(hst_reset),
133 .data_ready(adc_data_ready),
134 .data(raw_data),
135 .address(hst_addr),
136 .q(hst_q)
137 );
138
139 oscilloscope oscilloscope_unit (
140 .clk(CLK_50MHz),
141 .reset(osc_reset),
142 .data_ready(adc_data_ready),
143 .raw_data(raw_data),
144 .uwt_data(uwt_data),
145 .threshold(16'd100),
146 .address(osc_addr),
147 .start_address(osc_start_addr),
148 .q(osc_q)
149 );
150
151
152 always @ (posedge adc_clk)
153 begin
154 counter <= counter + 32'd1;
155 end
156
157 always @ (posedge CLK_50MHz)
158 begin
159 case (state0)
160 1:
161 begin
162 if (~adc_fifo_rdempty)
163 begin
164 adc_counter <= adc_counter + 32'd1;
165 adc_fifo_rdreq <= 1'b1;
166 adc_data_ready <= 1'b1;
167 state0 <= 4'd2;
168 end
169 end
170
171 2:
172 begin
173 adc_fifo_rdreq <= 1'b0;
174 adc_data_ready <= 1'b0;
175 state0 <= 4'd1;
176 end
177
178 default:
179 begin
180 state0 <= 4'd1;
181 end
182 endcase
183 end
184
185 always @ (posedge adc_clk)
186 begin
187 case (state2)
188 1:
189 begin
190 adc_data <= 12'd0;
191 state2 <= 4'd2;
192 end
193
194 2:
195 begin
196 adc_data <= 12'd1024;
197 state2 <= 4'd3;
198 end
199
200 3:
201 begin
202 adc_data <= 12'd2048;
203 state2 <= 4'd4;
204 end
205
206 4:
207 begin
208 adc_data <= 12'd3072;
209 state2 <= 4'd5;
210 end
211
212 5:
213 begin
214 adc_data <= 12'd4095;
215 state2 <= 4'd1;
216 end
217
218 default:
219 begin
220 state2 <= 4'd1;
221 end
222 endcase
223 end
224
225endmodule
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