source: trunk/3DEES/sys_pll.v@ 183

Last change on this file since 183 was 178, checked in by demin, 11 years ago

adapt to 6ch
File size: 5.6 KB
RevLine 
[84]1// megafunction wizard: %ALTPLL%
2// GENERATION: STANDARD
3// VERSION: WM1.0
4// MODULE: altpll
5
6// ============================================================
7// File Name: sys_pll.v
8// Megafunction Name(s):
9// altpll
10//
11// Simulation Library Files(s):
12// altera_mf
13// ============================================================
14// ************************************************************
15// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16//
17// 9.0 Build 132 02/25/2009 SJ Web Edition
18// ************************************************************
19
20
21//Copyright (C) 1991-2009 Altera Corporation
22//Your use of Altera Corporation's design tools, logic functions
23//and other software and tools, and its AMPP partner logic
24//functions, and any output files from any of the foregoing
25//(including device programming or simulation files), and any
26//associated documentation or information are expressly subject
27//to the terms and conditions of the Altera Program License
28//Subscription Agreement, Altera MegaCore Function License
29//Agreement, or other applicable license agreement, including,
30//without limitation, that your use is for the sole purpose of
31//programming logic devices manufactured by Altera and sold by
32//Altera or its authorized distributors. Please refer to the
33//applicable agreement for further details.
34
35
36// synopsys translate_off
37`timescale 1 ps / 1 ps
38// synopsys translate_on
39module sys_pll (
40 inclk0,
[178]41 c0,
42 c1,
43 c2);
[84]44
45 input inclk0;
46 output c0;
[178]47 output c1;
48 output c2;
[84]49
50 wire [4:0] sub_wire0;
[178]51 wire [0:0] sub_wire6 = 1'h0;
52 wire [2:2] sub_wire3 = sub_wire0[2:2];
53 wire [1:1] sub_wire2 = sub_wire0[1:1];
[84]54 wire [0:0] sub_wire1 = sub_wire0[0:0];
55 wire c0 = sub_wire1;
[178]56 wire c1 = sub_wire2;
57 wire c2 = sub_wire3;
58 wire sub_wire4 = inclk0;
59 wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
[84]60
61 altpll altpll_component (
[178]62 .inclk (sub_wire5),
[84]63 .clk (sub_wire0),
64 .activeclock (),
65 .areset (1'b0),
66 .clkbad (),
67 .clkena ({6{1'b1}}),
68 .clkloss (),
69 .clkswitch (1'b0),
70 .configupdate (1'b0),
71 .enable0 (),
72 .enable1 (),
73 .extclk (),
74 .extclkena ({4{1'b1}}),
75 .fbin (1'b1),
76 .fbmimicbidir (),
77 .fbout (),
[178]78 .fref (),
79 .icdrclk (),
[84]80 .locked (),
81 .pfdena (1'b1),
82 .phasecounterselect ({4{1'b1}}),
83 .phasedone (),
84 .phasestep (1'b1),
85 .phaseupdown (1'b1),
86 .pllena (1'b1),
87 .scanaclr (1'b0),
88 .scanclk (1'b0),
89 .scanclkena (1'b1),
90 .scandata (1'b0),
91 .scandataout (),
92 .scandone (),
93 .scanread (1'b0),
94 .scanwrite (1'b0),
95 .sclkout0 (),
96 .sclkout1 (),
97 .vcooverrange (),
98 .vcounderrange ());
99 defparam
100 altpll_component.bandwidth_type = "AUTO",
101 altpll_component.clk0_divide_by = 10,
102 altpll_component.clk0_duty_cycle = 50,
[178]103 altpll_component.clk0_multiply_by = 9,
[84]104 altpll_component.clk0_phase_shift = "0",
[178]105 altpll_component.clk1_divide_by = 10,
106 altpll_component.clk1_duty_cycle = 50,
107 altpll_component.clk1_multiply_by = 6,
108 altpll_component.clk1_phase_shift = "0",
109 altpll_component.clk2_divide_by = 10,
110 altpll_component.clk2_duty_cycle = 50,
111 altpll_component.clk2_multiply_by = 1,
112 altpll_component.clk2_phase_shift = "0",
[84]113 altpll_component.compensate_clock = "CLK0",
[178]114 altpll_component.inclk0_input_frequency = 10000,
[84]115 altpll_component.intended_device_family = "Cyclone III",
[178]116 altpll_component.lpm_hint = "CBX_MODULE_PREFIX=sys_pll",
[84]117 altpll_component.lpm_type = "altpll",
118 altpll_component.operation_mode = "NORMAL",
119 altpll_component.pll_type = "AUTO",
120 altpll_component.port_activeclock = "PORT_UNUSED",
121 altpll_component.port_areset = "PORT_UNUSED",
122 altpll_component.port_clkbad0 = "PORT_UNUSED",
123 altpll_component.port_clkbad1 = "PORT_UNUSED",
124 altpll_component.port_clkloss = "PORT_UNUSED",
125 altpll_component.port_clkswitch = "PORT_UNUSED",
126 altpll_component.port_configupdate = "PORT_UNUSED",
127 altpll_component.port_fbin = "PORT_UNUSED",
128 altpll_component.port_inclk0 = "PORT_USED",
129 altpll_component.port_inclk1 = "PORT_UNUSED",
130 altpll_component.port_locked = "PORT_UNUSED",
131 altpll_component.port_pfdena = "PORT_UNUSED",
132 altpll_component.port_phasecounterselect = "PORT_UNUSED",
133 altpll_component.port_phasedone = "PORT_UNUSED",
134 altpll_component.port_phasestep = "PORT_UNUSED",
135 altpll_component.port_phaseupdown = "PORT_UNUSED",
136 altpll_component.port_pllena = "PORT_UNUSED",
137 altpll_component.port_scanaclr = "PORT_UNUSED",
138 altpll_component.port_scanclk = "PORT_UNUSED",
139 altpll_component.port_scanclkena = "PORT_UNUSED",
140 altpll_component.port_scandata = "PORT_UNUSED",
141 altpll_component.port_scandataout = "PORT_UNUSED",
142 altpll_component.port_scandone = "PORT_UNUSED",
143 altpll_component.port_scanread = "PORT_UNUSED",
144 altpll_component.port_scanwrite = "PORT_UNUSED",
145 altpll_component.port_clk0 = "PORT_USED",
[178]146 altpll_component.port_clk1 = "PORT_USED",
147 altpll_component.port_clk2 = "PORT_USED",
[84]148 altpll_component.port_clk3 = "PORT_UNUSED",
149 altpll_component.port_clk4 = "PORT_UNUSED",
150 altpll_component.port_clk5 = "PORT_UNUSED",
151 altpll_component.port_clkena0 = "PORT_UNUSED",
152 altpll_component.port_clkena1 = "PORT_UNUSED",
153 altpll_component.port_clkena2 = "PORT_UNUSED",
154 altpll_component.port_clkena3 = "PORT_UNUSED",
155 altpll_component.port_clkena4 = "PORT_UNUSED",
156 altpll_component.port_clkena5 = "PORT_UNUSED",
157 altpll_component.port_extclk0 = "PORT_UNUSED",
158 altpll_component.port_extclk1 = "PORT_UNUSED",
159 altpll_component.port_extclk2 = "PORT_UNUSED",
160 altpll_component.port_extclk3 = "PORT_UNUSED",
161 altpll_component.width_clock = 5;
162
[178]163endmodule
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