source: trunk/3DEES/classifier.v@ 186

Last change on this file since 186 was 186, checked in by demin, 11 years ago

add fifth bin
File size: 6.7 KB
Line 
1module classifier
2 #(
3 parameter width = 12 // bit width of the input data (unsigned)
4 )
5 (
6 input wire clock, frame, reset,
7 input wire [22*width-1:0] cfg_data,
8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F}
9 input wire [5:0] inp_flag,
10 output wire [7:0] out_data,
11 output wire out_flag
12 );
13
14 reg out_flag_reg [2:0], out_flag_next [2:0];
15 reg [7:0] out_data_reg [2:0], out_data_next [2:0];
16 reg [5:0] inp_flag_reg, inp_flag_next;
17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0];
18 reg [15:0] int_pipe_reg [23:0], int_pipe_next [23:0];
19 reg [2:0] int_data_reg [3:0], int_data_next [3:0];
20 reg [4:0] int_temp_reg [1:0], int_temp_next [1:0];
21
22 wire [width-1:0] inp_data_wire [5:0];
23 wire [3:0] int_pipe_wire [5:0];
24 wire [19:0] int_comp_wire;
25
26 integer i;
27 genvar j;
28
29 generate
30 for (j = 0; j < 6; j = j + 1)
31 begin : CLASSIFIER_INPUT_DATA
32 assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
33 end
34 endgenerate
35
36 generate
37 assign int_comp_wire[0] = inp_flag_reg[0] & (inp_data_reg[0] < cfg_data[width-1:0]);
38 assign int_comp_wire[1] = inp_flag_reg[0] & (inp_data_reg[0] > cfg_data[2*width-1:1*width]) & (inp_data_reg[0] < cfg_data[3*width-1:2*width]);
39
40 assign int_comp_wire[2] = inp_flag_reg[1] & (inp_data_reg[1] < cfg_data[4*width-1:3*width]);
41 assign int_comp_wire[3] = inp_flag_reg[1] & (inp_data_reg[1] > cfg_data[5*width-1:4*width]) & (inp_data_reg[1] < cfg_data[6*width-1:5*width]);
42
43 for (j = 0; j < 4; j = j + 1)
44 begin : CLASSIFIER_COMPARTORS
45 assign int_comp_wire[j*4+0+4] = (inp_data_reg[j+2] > cfg_data[(j*4+0+6)*width+width-1:(j*4+0+6)*width]);
46 assign int_comp_wire[j*4+1+4] = (inp_data_reg[j+2] > cfg_data[(j*4+1+6)*width+width-1:(j*4+1+6)*width]);
47 assign int_comp_wire[j*4+2+4] = (inp_data_reg[j+2] > cfg_data[(j*4+2+6)*width+width-1:(j*4+2+6)*width]);
48 assign int_comp_wire[j*4+3+4] = (inp_data_reg[j+2] > cfg_data[(j*4+3+6)*width+width-1:(j*4+3+6)*width]);
49 end
50 endgenerate
51
52 generate
53 for (j = 0; j < 4; j = j + 1)
54 begin : CLASSIFIER_PIPELINE
55 assign int_pipe_wire[0][j] = (|int_pipe_reg[j]);
56 assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]);
57 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*4+0+8]);
58 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*4+1+8]);
59 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*4+2+8]);
60 assign int_pipe_wire[j+2][3] = (|int_pipe_reg[j*4+3+8]);
61 end
62 endgenerate
63
64 always @(posedge clock)
65 begin
66 if (reset)
67 begin
68 inp_flag_reg <= {(6){1'b0}};
69 for (i = 0; i < 3; i = i + 1)
70 begin
71 out_data_reg[i] <= {(7){1'b0}};
72 out_flag_reg[i] <= 1'b0;
73 end
74 for (i = 0; i < 6; i = i + 1)
75 begin
76 inp_data_reg[i] <= {(width){1'b0}};
77 end
78 for (i = 0; i < 24; i = i + 1)
79 begin
80 int_pipe_reg[i] <= {(16){1'b0}};
81 end
82 for (i = 0; i < 4; i = i + 1)
83 begin
84 int_data_reg[i] <= {(3){1'b0}};
85 end
86 for (i = 0; i < 2; i = i + 1)
87 begin
88 int_temp_reg[i] <= {(5){1'b0}};
89 end
90 end
91 else
92 begin
93 inp_flag_reg <= inp_flag_next;
94 for (i = 0; i < 3; i = i + 1)
95 begin
96 out_data_reg[i] <= out_data_next[i];
97 out_flag_reg[i] <= out_flag_next[i];
98 end
99 for (i = 0; i < 6; i = i + 1)
100 begin
101 inp_data_reg[i] <= inp_data_next[i];
102 end
103 for (i = 0; i < 24; i = i + 1)
104 begin
105 int_pipe_reg[i] <= int_pipe_next[i];
106 end
107 for (i = 0; i < 4; i = i + 1)
108 begin
109 int_data_reg[i] <= int_data_next[i];
110 end
111 for (i = 0; i < 2; i = i + 1)
112 begin
113 int_temp_reg[i] <= int_temp_next[i];
114 end
115 end
116 end
117
118 always @*
119 begin
120 inp_flag_next = inp_flag_reg;
121 for (i = 0; i < 3; i = i + 1)
122 begin
123 out_data_next[i] = out_data_reg[i];
124 out_flag_next[i] = out_flag_reg[i];
125 end
126 for (i = 0; i < 6; i = i + 1)
127 begin
128 inp_data_next[i] = inp_data_reg[i];
129 end
130 for (i = 0; i < 24; i = i + 1)
131 begin
132 int_pipe_next[i] = int_pipe_reg[i];
133 end
134 for (i = 0; i < 4; i = i + 1)
135 begin
136 int_data_next[i] = int_data_reg[i];
137 end
138 for (i = 0; i < 2; i = i + 1)
139 begin
140 int_temp_next[i] = int_temp_reg[i];
141 end
142
143 if (frame)
144 begin
145 inp_flag_next = inp_flag;
146 for (i = 0; i < 6; i = i + 1)
147 begin
148 inp_data_next[i] = inp_data_wire[i];
149 end
150
151 if (out_flag_reg[2])
152 begin
153 for (i = 0; i < 3; i = i + 1)
154 begin
155 out_data_next[i] = {(7){1'b0}};
156 out_flag_next[i] = 1'b0;
157 end
158 for (i = 0; i < 24; i = i + 1)
159 begin
160 int_pipe_next[i] = {(16){1'b0}};
161 end
162 int_temp_next[0] = {(5){1'b0}};
163 int_temp_next[1] = {(5){1'b0}};
164 end
165 else
166 begin
167 out_data_next[0] = {(7){1'b0}};
168 out_data_next[1] = out_data_reg[0];
169 out_data_next[2] = out_data_reg[1];
170
171 out_flag_next[0] = 1'b1;
172 out_flag_next[1] = out_flag_reg[0];
173 out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]);
174
175 for (i = 0; i < 5; i = i + 1)
176 begin
177 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]};
178 end
179 for (i = 4; i < 8; i = i + 1)
180 begin
181 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]};
182 end
183 for (i = 8; i < 24; i = i + 1)
184 begin
185 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-4]};
186 end
187
188 for (i = 0; i < 4; i = i + 1)
189 begin
190 case (int_pipe_wire[i+2][3:0])
191 4'b0000: int_data_next[i] = 3'b000;
192 4'b0001: int_data_next[i] = 3'b001;
193 4'b0011: int_data_next[i] = 3'b010;
194 4'b0111: int_data_next[i] = 3'b011;
195 4'b1111: int_data_next[i] = 3'b100;
196 default: int_data_next[i] = 3'b000;
197 endcase
198 end
199
200 int_temp_next[0] = {int_pipe_wire[1], ^int_pipe_wire[0]};
201 int_temp_next[1] = {1'b0, int_pipe_wire[0]};
202
203 case (int_temp_reg[0][4:0])
204 5'b00011: out_data_next[0][4:0] = int_data_next[0];
205 5'b00111: out_data_next[0][4:0] = int_data_next[1] + 4'd5;
206 5'b01111: out_data_next[0][4:0] = int_data_next[2] + 4'd10;
207 5'b11111: out_data_next[0][4:0] = int_data_next[3] + 4'd15;
208 default: out_flag_next[0] = 1'b0;
209 endcase
210
211 case (int_temp_reg[1][3:0])
212 // S1_F, electron
213 4'b0001: out_data_next[0][7:5] = 3'b100;
214
215 // S1_F, proton
216 4'b0010: out_data_next[0][7:5] = 3'b101;
217
218 // S1_S, electron
219 4'b0100: out_data_next[0][7:5] = 3'b110;
220
221 // S1_S, proton
222 4'b1000: out_data_next[0][7:5] = 3'b111;
223
224 default: out_flag_next[0] = 1'b0;
225 endcase
226 end
227 end
228 end
229
230// assign out_data = {1'd0, int_pipe_wire[1+2][2:0], int_data_reg[1]};
231// assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]};
232// assign out_data = {1'd0, int_temp_reg[0][4:0]};
233 assign out_data = out_data_reg[2];
234 assign out_flag = out_flag_reg[2];
235
236endmodule
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