source: trunk/3DEES/amplitude.v@ 192

Last change on this file since 192 was 180, checked in by demin, 11 years ago

add classifier and remove unneeded modules

File size: 3.0 KB
Line 
1module amplitude
2 #(
3 parameter width = 12 // bit width of the input data
4 )
5 (
6 input wire clock, frame, reset,
7 input wire [width-1:0] min_data,
8 input wire [width-1:0] max_data,
9 input wire [width-1:0] inp_data,
10 output wire [width-1:0] out_data,
11 output wire [1:0] out_flag
12 );
13
14 reg int_case_reg, int_case_next;
15 reg out_flag_reg, out_flag_next;
16 reg int_flag_reg, int_flag_next;
17 reg [width-1:0] int_mini_reg, int_mini_next;
18 reg [width-1:0] out_data_reg, out_data_next;
19 reg [width-1:0] inp_data_reg [1:0], inp_data_next [1:0];
20
21 wire [1:0] int_comp_wire;
22 reg int_comp_reg, int_comp_next;
23
24 reg [5:0] int_cntr_reg, int_cntr_next;
25
26 assign int_comp_wire[0] = (inp_data_reg[1] < inp_data);
27 assign int_comp_wire[1] = (inp_data_reg[1] < max_data);
28
29 always @(posedge clock)
30 begin
31 if (reset)
32 begin
33 int_case_reg <= 1'b0;
34 int_mini_reg <= {(width){1'b0}};
35 inp_data_reg[0] <= {(width){1'b0}};
36 inp_data_reg[1] <= {(width){1'b0}};
37 out_data_reg <= {(width){1'b0}};
38 out_flag_reg <= 1'b0;
39 int_flag_reg <= 1'b0;
40 int_comp_reg <= 1'b0;
41 int_cntr_reg <= 6'd0;
42 end
43 else
44 begin
45 int_case_reg <= int_case_next;
46 int_mini_reg <= int_mini_next;
47 inp_data_reg[0] <= inp_data_next[0];
48 inp_data_reg[1] <= inp_data_next[1];
49 out_data_reg <= out_data_next;
50 out_flag_reg <= out_flag_next;
51 int_flag_reg <= int_flag_next;
52 int_comp_reg <= int_comp_next;
53 int_cntr_reg <= int_cntr_next;
54 end
55 end
56
57 always @*
58 begin
59 int_case_next = int_case_reg;
60 int_mini_next = int_mini_reg;
61 inp_data_next[0] = inp_data_reg[0];
62 inp_data_next[1] = inp_data_reg[1];
63 out_data_next = out_data_reg;
64 out_flag_next = out_flag_reg;
65 int_flag_next = int_flag_reg;
66 int_comp_next = int_comp_reg;
67 int_cntr_next = int_cntr_reg;
68
69 case (int_case_reg)
70 0:
71 begin
72 if (frame)
73 begin
74 inp_data_next[0] = inp_data;
75 inp_data_next[1] = inp_data_reg[0];
76 int_comp_next = int_comp_wire[0];
77 out_data_next = {(width){1'b0}};
78 out_flag_next = 1'b0;
79 // minimum
80 if ((~int_comp_reg) & (int_comp_wire[0]) & int_cntr_reg[5])
81 begin
82 int_mini_next = inp_data_reg[0];
83 int_flag_next = 1'b1;
84 end
85 // maximum after minimum
86 else if ((int_comp_reg) & (~int_comp_wire[0]) & (int_flag_reg))
87 begin
88 out_data_next = inp_data_reg[0] - int_mini_reg;
89// int_flag_next = 1'b0;
90 int_case_next = 1'b1;
91 end
92 else if (~int_cntr_reg[5])
93 begin
94 int_cntr_next = int_cntr_reg + 6'd1;
95 end
96 end
97 end
98
99 1:
100 begin
101 if (out_data_reg > min_data)
102 begin
103 int_cntr_next = 6'b0;
104// out_flag_next = 1'b1;
105 out_flag_next = int_comp_wire[1];
106 int_flag_next = ~int_comp_wire[1];
107 end
108 int_case_next = 1'b0;
109 end
110
111 endcase
112 end
113
114 assign out_data = out_data_reg;
115 assign out_flag = {~int_cntr_reg[5], out_flag_reg};
116
117endmodule
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