source: trunk/3DEES/adc_lvds.v@ 200

Last change on this file since 200 was 178, checked in by demin, 11 years ago

adapt to 6ch

File size: 3.2 KB
Line 
1
2(* ALTERA_ATTRIBUTE = {"{-to int_data_p} DDIO_INPUT_REGISTER=HIGH; {-to int_data_n} DDIO_INPUT_REGISTER=LOW"} *)
3
4module adc_lvds
5 #(
6 parameter size = 3, // number of channels
7 parameter width = 12 // channel resolution
8 )
9 (
10 input wire clock,
11
12 input wire lvds_dco,
13 input wire lvds_fco,
14 input wire [size-1:0] lvds_d,
15 input wire [11:0] test,
16
17 output wire adc_frame,
18 output wire [size*width-1:0] adc_data
19
20 );
21 localparam width2 = width + 2;
22
23
24 reg state, int_rdreq, adc_frame_reg;
25 wire int_wrfull, int_rdempty;
26
27 reg [size-1:0] int_data_p, int_data_n;
28
29 reg [2:0] int_edge_reg;
30
31 reg [size*width-1:0] int_fifo_reg;
32 wire [size*width-1:0] int_fifo_wire;
33
34 reg [size*width2-1:0] int_data_reg;
35 wire [size*width2-1:0] int_data_wire;
36
37 wire [size*width-1:0] int_q_wire;
38 reg [size*width-1:0] adc_data_reg;
39
40
41
42 genvar j;
43
44 generate
45 for (j = 0; j < size; j = j + 1)
46 begin : INT_DATA
47// MSB first
48// assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_p[j], int_data_n[j]};
49// LSB first
50// assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]};
51
52// assign int_fifo_wire[j*width+width-1:j*width] = test;
53
54 assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_reg[j*width2+width2-3:j*width2], int_data_p[j], int_data_n[j]};
55 assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-1:j*width2+2];
56// assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-1:j*width2+8];
57
58// assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]};
59// assign [j*width+width-1:j*width] = int_data_reg[j*width2+width2-3:j*width2];
60 end
61 endgenerate
62
63
64 dcfifo #(
65 .intended_device_family("Cyclone III"),
66 .lpm_numwords(16),
67 .lpm_showahead("ON"),
68 .lpm_type("dcfifo"),
69 .lpm_width(size*width),
70 .lpm_widthu(4),
71 .rdsync_delaypipe(4),
72 .wrsync_delaypipe(4),
73 .overflow_checking("ON"),
74 .underflow_checking("ON"),
75 .use_eab("ON")) fifo_unit (
76// .data(int_data_wire),
77 .data(int_fifo_reg),
78 .rdclk(clock),
79 .rdreq((~int_rdempty) & int_rdreq),
80 .wrclk(lvds_fco),
81 .wrreq(~int_wrfull),
82 .q(int_q_wire),
83 .rdempty(int_rdempty),
84 .wrfull(int_wrfull),
85 .aclr(),
86 .rdfull(),
87 .rdusedw(),
88 .wrempty(),
89 .wrusedw());
90
91 always @ (posedge clock)
92 begin
93 case (state)
94 1'b0:
95 begin
96 int_rdreq <= 1'b1;
97 adc_frame_reg <= 1'b0;
98 state <= 1'b1;
99 end
100
101 1'b1:
102 begin
103 if (~int_rdempty)
104 begin
105 int_rdreq <= 1'b0;
106 adc_frame_reg <= 1'b1;
107 adc_data_reg <= int_q_wire;
108 state <= 1'b0;
109 end
110 end
111 endcase
112 end
113
114 always @ (negedge lvds_dco)
115 begin
116 int_data_n <= lvds_d;
117 end
118
119 always @ (posedge lvds_dco)
120 begin
121 int_data_p <= lvds_d;
122 int_data_reg <= int_data_wire;
123 int_edge_reg <= {(~int_edge_reg[1]), int_edge_reg[0], lvds_fco};
124 if (int_edge_reg[1] & int_edge_reg[2])
125 begin
126 int_fifo_reg <= int_fifo_wire;
127 end
128 end
129
130 assign adc_frame = adc_frame_reg;
131 assign adc_data = adc_data_reg;
132
133endmodule
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