Last change
on this file since 107 was 107, checked in by demin, 14 years ago |
Starting to test signal shaping algorithms
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File size:
1.1 KB
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Rev | Line | |
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[59] | 1 | module test
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| 2 | (
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[107] | 3 | input wire clock,
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[84] | 4 | output wire [11:0] data
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[59] | 5 | );
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| 6 |
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[107] | 7 | reg [11:0] int_addr;
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[59] | 8 |
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[107] | 9 | always @(posedge clock)
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[59] | 10 | begin
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[107] | 11 | if (int_addr == 12'd2559)
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| 12 | begin
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| 13 | int_addr <= 12'd0;
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| 14 | end
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| 15 | else
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| 16 | begin
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| 17 | int_addr <= int_addr + 12'd1;
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| 18 | end
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[59] | 19 |
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| 20 | end
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| 21 |
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[107] | 22 | altsyncram #(
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| 23 | .address_aclr_a("NONE"),
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| 24 | .clock_enable_input_a("BYPASS"),
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| 25 | .clock_enable_output_a("BYPASS"),
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| 26 | .init_file("test_mwd.mif"),
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| 27 | .intended_device_family("Cyclone III"),
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| 28 | .lpm_hint("ENABLE_RUNTIME_MOD=NO"),
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| 29 | .lpm_type("altsyncram"),
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| 30 | .numwords_a(2560),
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| 31 | .operation_mode("ROM"),
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| 32 | .outdata_aclr_a("NONE"),
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| 33 | .outdata_reg_a("CLOCK0"),
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| 34 | .widthad_a(12),
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| 35 | .width_a(12),
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| 36 | .width_byteena_a(1)) test_rom_unit (
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| 37 | .clock0(clock),
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| 38 | .address_a(int_addr),
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| 39 | .q_a(data),
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| 40 | .aclr0(1'b0),
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| 41 | .aclr1(1'b0),
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| 42 | .address_b(1'b1),
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| 43 | .addressstall_a(1'b0),
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| 44 | .addressstall_b(1'b0),
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| 45 | .byteena_a(1'b1),
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| 46 | .byteena_b(1'b1),
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| 47 | .clock1(1'b1),
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| 48 | .clocken0(1'b1),
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| 49 | .clocken1(1'b1),
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| 50 | .clocken2(1'b1),
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| 51 | .clocken3(1'b1),
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| 52 | .data_a({12{1'b1}}),
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| 53 | .data_b(1'b1),
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| 54 | .eccstatus(),
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| 55 | .q_b(),
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| 56 | .rden_a(1'b1),
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| 57 | .rden_b(1'b1),
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| 58 | .wren_a(1'b0),
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| 59 | .wren_b(1'b0));
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[59] | 60 |
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| 61 | endmodule
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