[128] | 1 | module new_filter
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| 2 | #(
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| 3 | parameter size = 3, // number of channels
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| 4 | parameter width = 12 // bit width of the input data (unsigned)
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| 5 | )
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| 6 | (
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| 7 | input wire clock, frame, reset,
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| 8 | input wire [size*width-1:0] inp_data,
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| 9 | output wire [size*widthr-1:0] out_data
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| 10 | );
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| 11 |
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| 12 | localparam widthr = width + 9;
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| 13 | /*
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| 14 | 4-bit LFSR with additional bits to keep track of previous values
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| 15 | */
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| 16 | reg [15:0] int_lfsr_reg, int_lfsr_next;
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| 17 |
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| 18 | reg int_wren_reg, int_wren_next;
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| 19 | reg int_flag_reg, int_flag_next;
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| 20 | reg [1:0] int_chan_reg, int_chan_next;
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| 21 | reg [2:0] int_case_reg, int_case_next;
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| 22 | reg [5:0] int_addr_reg, int_addr_next;
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| 23 |
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| 24 | wire [5:0] int_addr_wire;
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| 25 |
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| 26 | reg [size*widthr-1:0] acc_data_reg [1:0], acc_data_next [1:0];
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| 27 | reg [size*widthr-1:0] int_data_reg [4:0], int_data_next [4:0];
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| 28 |
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| 29 | wire [size*widthr-1:0] acc_data_wire [1:0], del_data_wire;
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| 30 |
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| 31 | integer i;
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| 32 | genvar j;
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| 33 |
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| 34 | generate
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| 35 | for (j = 0; j < size; j = j + 1)
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| 36 | begin : INT_DATA
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| 37 | assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
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| 38 |
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| 39 | assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
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| 40 | acc_data_reg[0][j*widthr+widthr-1:j*widthr]
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| 41 | - del_data_wire[j*widthr+widthr-1:j*widthr]
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| 42 | + acc_data_reg[1][j*widthr+widthr-1:j*widthr];
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| 43 |
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| 44 | end
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| 45 | endgenerate
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| 46 |
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| 47 | altsyncram #(
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| 48 | .address_aclr_b("NONE"),
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| 49 | .address_reg_b("CLOCK0"),
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| 50 | .clock_enable_input_a("BYPASS"),
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| 51 | .clock_enable_input_b("BYPASS"),
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| 52 | .clock_enable_output_b("BYPASS"),
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| 53 | .intended_device_family("Cyclone III"),
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| 54 | .lpm_type("altsyncram"),
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| 55 | .numwords_a(64),
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| 56 | .numwords_b(64),
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| 57 | .operation_mode("DUAL_PORT"),
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| 58 | .outdata_aclr_b("NONE"),
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| 59 | .outdata_reg_b("CLOCK0"),
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| 60 | .power_up_uninitialized("FALSE"),
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| 61 | .read_during_write_mode_mixed_ports("DONT_CARE"),
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| 62 | .widthad_a(6),
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| 63 | .widthad_b(6),
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| 64 | .width_a(size*widthr),
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| 65 | .width_b(size*widthr),
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| 66 | .width_byteena_a(1)) ram_unit_1 (
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| 67 | .wren_a(int_wren_reg),
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| 68 | .clock0(clock),
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| 69 | .address_a(int_addr_reg),
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| 70 | .address_b(int_addr_wire),
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| 71 | .data_a(acc_data_reg[0]),
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| 72 | .q_b(del_data_wire),
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| 73 | .aclr0(1'b0),
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| 74 | .aclr1(1'b0),
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| 75 | .addressstall_a(1'b0),
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| 76 | .addressstall_b(1'b0),
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| 77 | .byteena_a(1'b1),
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| 78 | .byteena_b(1'b1),
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| 79 | .clock1(1'b1),
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| 80 | .clocken0(1'b1),
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| 81 | .clocken1(1'b1),
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| 82 | .clocken2(1'b1),
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| 83 | .clocken3(1'b1),
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| 84 | .data_b({(size*widthr){1'b1}}),
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| 85 | .eccstatus(),
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| 86 | .q_a(),
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| 87 | .rden_a(1'b1),
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| 88 | .rden_b(1'b1),
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| 89 | .wren_b(1'b0));
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| 90 |
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| 91 | lpm_mux #(
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| 92 | .lpm_size(4),
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| 93 | .lpm_type("LPM_MUX"),
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| 94 | .lpm_width(6),
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| 95 | .lpm_widths(2)) mux_unit_1 (
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| 96 | .sel(int_chan_next),
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| 97 | .data({
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| 98 | 2'd3, int_lfsr_reg[5+3:5],
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| 99 | 2'd2, int_lfsr_reg[4+3:4],
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| 100 | 2'd1, int_lfsr_reg[4+3:4],
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| 101 | 2'd0, int_lfsr_reg[3+3:3]}),
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| 102 | .result(int_addr_wire));
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| 103 |
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| 104 | always @(posedge clock)
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| 105 | begin
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| 106 | if (reset)
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| 107 | begin
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| 108 | int_wren_reg <= 1'b1;
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| 109 | int_flag_reg <= 1'b0;
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| 110 | int_chan_reg <= 2'd0;
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| 111 | int_case_reg <= 3'd0;
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| 112 | int_addr_reg <= 6'd0;
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| 113 | for(i = 0; i <= 1; i = i + 1)
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| 114 | begin
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| 115 | acc_data_reg[i] <= {(size*widthr){1'b0}};
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| 116 | end
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| 117 | for(i = 0; i <= 4; i = i + 1)
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| 118 | begin
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| 119 | int_data_reg[i] <= {(size*widthr){1'b0}};
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| 120 | end
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| 121 | int_lfsr_reg <= 16'd0;
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| 122 | end
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| 123 | else
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| 124 | begin
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| 125 | int_wren_reg <= int_wren_next;
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| 126 | int_flag_reg <= int_flag_next;
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| 127 | int_chan_reg <= int_chan_next;
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| 128 | int_case_reg <= int_case_next;
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| 129 | int_addr_reg <= int_addr_next;
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| 130 | for(i = 0; i <= 1; i = i + 1)
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| 131 | begin
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| 132 | acc_data_reg[i] <= acc_data_next[i];
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| 133 | end
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| 134 | for(i = 0; i <= 4; i = i + 1)
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| 135 | begin
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| 136 | int_data_reg[i] <= int_data_next[i];
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| 137 | end
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| 138 | int_lfsr_reg <= int_lfsr_next;
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| 139 | end
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| 140 | end
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| 141 |
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| 142 | always @*
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| 143 | begin
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| 144 | int_wren_next = int_wren_reg;
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| 145 | int_flag_next = int_flag_reg;
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| 146 | int_chan_next = int_chan_reg;
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| 147 | int_case_next = int_case_reg;
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| 148 | int_addr_next = int_addr_reg;
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| 149 | for(i = 0; i <= 1; i = i + 1)
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| 150 | begin
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| 151 | acc_data_next[i] = acc_data_reg[i];
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| 152 | end
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| 153 | for(i = 0; i <= 4; i = i + 1)
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| 154 | begin
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| 155 | int_data_next[i] = int_data_reg[i];
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| 156 | end
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| 157 | int_lfsr_next = int_lfsr_reg;
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| 158 |
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| 159 | case (int_case_reg)
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| 160 | 0:
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| 161 | begin
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| 162 | // write zeros
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| 163 | int_wren_next = 1'b1;
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| 164 | int_addr_next = 6'd0;
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| 165 | for(i = 0; i <= 1; i = i + 1)
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| 166 | begin
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| 167 | acc_data_next[i] = {(size*widthr){1'b0}};
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| 168 | end
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| 169 | for(i = 0; i <= 4; i = i + 1)
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| 170 | begin
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| 171 | int_data_next[i] = {(size*widthr){1'b0}};
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| 172 | end
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| 173 | int_case_next = 3'd1;
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| 174 | end
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| 175 | 1:
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| 176 | begin
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| 177 | // write zeros
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| 178 | int_addr_next = int_addr_reg + 6'd1;
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| 179 | if (&int_addr_reg)
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| 180 | begin
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| 181 | int_wren_next = 1'b0;
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| 182 | int_flag_next = 1'b0;
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| 183 | int_chan_next = 2'd0;
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| 184 | int_lfsr_next = 16'h7650;
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| 185 | int_case_next = 3'd2;
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| 186 | end
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| 187 | end
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| 188 | 2: // frame
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| 189 | begin
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| 190 | int_flag_next = 1'b0;
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| 191 | if (frame)
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| 192 | begin
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| 193 | int_wren_next = 1'b1;
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| 194 |
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| 195 | int_addr_next = {2'd0, int_lfsr_reg[3:0]};
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| 196 |
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| 197 | // set read addr for 2nd pipeline
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| 198 | int_chan_next = 2'd1;
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| 199 |
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| 200 | // prepare registers for 1st sum
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| 201 | acc_data_next[0] = acc_data_wire[0];
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| 202 | acc_data_next[1] = int_data_reg[0];
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| 203 |
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| 204 | int_case_next = 3'd3;
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| 205 | end
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| 206 | if (int_flag_reg) // register 4th sum
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| 207 | begin
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| 208 | // register 4th sum
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| 209 | int_data_next[3] = acc_data_wire[1];
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| 210 | end
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| 211 | end
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| 212 | 3: // 1st sum
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| 213 | begin
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| 214 | int_addr_next = {2'd1, int_lfsr_reg[3:0]};
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| 215 |
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| 216 | // set read addr for 3rd pipeline
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| 217 | int_chan_next = 2'd2;
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| 218 |
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| 219 | // prepare registers for 2nd sum
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| 220 | acc_data_next[0] = int_data_reg[0];
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| 221 | acc_data_next[1] = int_data_reg[1];
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| 222 |
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| 223 | // register 1st sum
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| 224 | int_data_next[0] = acc_data_wire[1];
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| 225 |
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| 226 | int_case_next = 3'd4;
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| 227 | end
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| 228 | 4: // 2nd sum
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| 229 | begin
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| 230 | int_addr_next = {2'd2, int_lfsr_reg[3:0]};
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| 231 |
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| 232 | // set read addr for 4th pipeline
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| 233 | int_chan_next = 2'd3;
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| 234 |
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| 235 | // prepare registers for 3rd sum
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| 236 | acc_data_next[0] = int_data_reg[1];
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| 237 | acc_data_next[1] = int_data_reg[2];
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| 238 |
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| 239 | // register 2nd sum
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| 240 | int_data_next[1] = acc_data_wire[1];
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| 241 |
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| 242 | int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]};
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| 243 |
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| 244 | int_case_next = 3'd5;
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| 245 | end
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| 246 | 5: // 3rd sum
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| 247 | begin
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| 248 | int_flag_next = 1'b1;
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| 249 |
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| 250 | int_addr_next = {2'd3, int_lfsr_reg[4:1]};
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| 251 |
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| 252 | // set read addr for 1st pipeline
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| 253 | int_chan_next = 2'd0;
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| 254 |
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| 255 | // prepare registers for 4th sum
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| 256 | acc_data_next[0] = int_data_reg[2];
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| 257 | acc_data_next[1] = int_data_reg[3];
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| 258 |
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| 259 | // register 3rd sum
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| 260 | int_data_next[2] = acc_data_wire[1];
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| 261 |
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| 262 | // register 4th output
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| 263 | int_data_next[4] = int_data_reg[3];
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| 264 |
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| 265 | int_case_next = 3'd2;
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| 266 | end
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| 267 | default:
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| 268 | begin
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| 269 | int_case_next = 3'd0;
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| 270 | end
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| 271 | endcase
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| 272 | end
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| 273 |
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| 274 | assign out_data = int_data_reg[4];
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| 275 |
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| 276 | endmodule
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