source: sandbox/MultiChannelUSB/new_filter.v

Last change on this file was 128, checked in by demin, 15 years ago

add short filter with sufficient noise suppression
File size: 6.5 KB
Line 
1module new_filter
2 #(
3 parameter size = 3, // number of channels
4 parameter width = 12 // bit width of the input data (unsigned)
5 )
6 (
7 input wire clock, frame, reset,
8 input wire [size*width-1:0] inp_data,
9 output wire [size*widthr-1:0] out_data
10 );
11
12 localparam widthr = width + 9;
13 /*
14 4-bit LFSR with additional bits to keep track of previous values
15 */
16 reg [15:0] int_lfsr_reg, int_lfsr_next;
17
18 reg int_wren_reg, int_wren_next;
19 reg int_flag_reg, int_flag_next;
20 reg [1:0] int_chan_reg, int_chan_next;
21 reg [2:0] int_case_reg, int_case_next;
22 reg [5:0] int_addr_reg, int_addr_next;
23
24 wire [5:0] int_addr_wire;
25
26 reg [size*widthr-1:0] acc_data_reg [1:0], acc_data_next [1:0];
27 reg [size*widthr-1:0] int_data_reg [4:0], int_data_next [4:0];
28
29 wire [size*widthr-1:0] acc_data_wire [1:0], del_data_wire;
30
31 integer i;
32 genvar j;
33
34 generate
35 for (j = 0; j < size; j = j + 1)
36 begin : INT_DATA
37 assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
38
39 assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
40 acc_data_reg[0][j*widthr+widthr-1:j*widthr]
41 - del_data_wire[j*widthr+widthr-1:j*widthr]
42 + acc_data_reg[1][j*widthr+widthr-1:j*widthr];
43
44 end
45 endgenerate
46
47 altsyncram #(
48 .address_aclr_b("NONE"),
49 .address_reg_b("CLOCK0"),
50 .clock_enable_input_a("BYPASS"),
51 .clock_enable_input_b("BYPASS"),
52 .clock_enable_output_b("BYPASS"),
53 .intended_device_family("Cyclone III"),
54 .lpm_type("altsyncram"),
55 .numwords_a(64),
56 .numwords_b(64),
57 .operation_mode("DUAL_PORT"),
58 .outdata_aclr_b("NONE"),
59 .outdata_reg_b("CLOCK0"),
60 .power_up_uninitialized("FALSE"),
61 .read_during_write_mode_mixed_ports("DONT_CARE"),
62 .widthad_a(6),
63 .widthad_b(6),
64 .width_a(size*widthr),
65 .width_b(size*widthr),
66 .width_byteena_a(1)) ram_unit_1 (
67 .wren_a(int_wren_reg),
68 .clock0(clock),
69 .address_a(int_addr_reg),
70 .address_b(int_addr_wire),
71 .data_a(acc_data_reg[0]),
72 .q_b(del_data_wire),
73 .aclr0(1'b0),
74 .aclr1(1'b0),
75 .addressstall_a(1'b0),
76 .addressstall_b(1'b0),
77 .byteena_a(1'b1),
78 .byteena_b(1'b1),
79 .clock1(1'b1),
80 .clocken0(1'b1),
81 .clocken1(1'b1),
82 .clocken2(1'b1),
83 .clocken3(1'b1),
84 .data_b({(size*widthr){1'b1}}),
85 .eccstatus(),
86 .q_a(),
87 .rden_a(1'b1),
88 .rden_b(1'b1),
89 .wren_b(1'b0));
90
91 lpm_mux #(
92 .lpm_size(4),
93 .lpm_type("LPM_MUX"),
94 .lpm_width(6),
95 .lpm_widths(2)) mux_unit_1 (
96 .sel(int_chan_next),
97 .data({
98 2'd3, int_lfsr_reg[5+3:5],
99 2'd2, int_lfsr_reg[4+3:4],
100 2'd1, int_lfsr_reg[4+3:4],
101 2'd0, int_lfsr_reg[3+3:3]}),
102 .result(int_addr_wire));
103
104 always @(posedge clock)
105 begin
106 if (reset)
107 begin
108 int_wren_reg <= 1'b1;
109 int_flag_reg <= 1'b0;
110 int_chan_reg <= 2'd0;
111 int_case_reg <= 3'd0;
112 int_addr_reg <= 6'd0;
113 for(i = 0; i <= 1; i = i + 1)
114 begin
115 acc_data_reg[i] <= {(size*widthr){1'b0}};
116 end
117 for(i = 0; i <= 4; i = i + 1)
118 begin
119 int_data_reg[i] <= {(size*widthr){1'b0}};
120 end
121 int_lfsr_reg <= 16'd0;
122 end
123 else
124 begin
125 int_wren_reg <= int_wren_next;
126 int_flag_reg <= int_flag_next;
127 int_chan_reg <= int_chan_next;
128 int_case_reg <= int_case_next;
129 int_addr_reg <= int_addr_next;
130 for(i = 0; i <= 1; i = i + 1)
131 begin
132 acc_data_reg[i] <= acc_data_next[i];
133 end
134 for(i = 0; i <= 4; i = i + 1)
135 begin
136 int_data_reg[i] <= int_data_next[i];
137 end
138 int_lfsr_reg <= int_lfsr_next;
139 end
140 end
141
142 always @*
143 begin
144 int_wren_next = int_wren_reg;
145 int_flag_next = int_flag_reg;
146 int_chan_next = int_chan_reg;
147 int_case_next = int_case_reg;
148 int_addr_next = int_addr_reg;
149 for(i = 0; i <= 1; i = i + 1)
150 begin
151 acc_data_next[i] = acc_data_reg[i];
152 end
153 for(i = 0; i <= 4; i = i + 1)
154 begin
155 int_data_next[i] = int_data_reg[i];
156 end
157 int_lfsr_next = int_lfsr_reg;
158
159 case (int_case_reg)
160 0:
161 begin
162 // write zeros
163 int_wren_next = 1'b1;
164 int_addr_next = 6'd0;
165 for(i = 0; i <= 1; i = i + 1)
166 begin
167 acc_data_next[i] = {(size*widthr){1'b0}};
168 end
169 for(i = 0; i <= 4; i = i + 1)
170 begin
171 int_data_next[i] = {(size*widthr){1'b0}};
172 end
173 int_case_next = 3'd1;
174 end
175 1:
176 begin
177 // write zeros
178 int_addr_next = int_addr_reg + 6'd1;
179 if (&int_addr_reg)
180 begin
181 int_wren_next = 1'b0;
182 int_flag_next = 1'b0;
183 int_chan_next = 2'd0;
184 int_lfsr_next = 16'h7650;
185 int_case_next = 3'd2;
186 end
187 end
188 2: // frame
189 begin
190 int_flag_next = 1'b0;
191 if (frame)
192 begin
193 int_wren_next = 1'b1;
194
195 int_addr_next = {2'd0, int_lfsr_reg[3:0]};
196
197 // set read addr for 2nd pipeline
198 int_chan_next = 2'd1;
199
200 // prepare registers for 1st sum
201 acc_data_next[0] = acc_data_wire[0];
202 acc_data_next[1] = int_data_reg[0];
203
204 int_case_next = 3'd3;
205 end
206 if (int_flag_reg) // register 4th sum
207 begin
208 // register 4th sum
209 int_data_next[3] = acc_data_wire[1];
210 end
211 end
212 3: // 1st sum
213 begin
214 int_addr_next = {2'd1, int_lfsr_reg[3:0]};
215
216 // set read addr for 3rd pipeline
217 int_chan_next = 2'd2;
218
219 // prepare registers for 2nd sum
220 acc_data_next[0] = int_data_reg[0];
221 acc_data_next[1] = int_data_reg[1];
222
223 // register 1st sum
224 int_data_next[0] = acc_data_wire[1];
225
226 int_case_next = 3'd4;
227 end
228 4: // 2nd sum
229 begin
230 int_addr_next = {2'd2, int_lfsr_reg[3:0]};
231
232 // set read addr for 4th pipeline
233 int_chan_next = 2'd3;
234
235 // prepare registers for 3rd sum
236 acc_data_next[0] = int_data_reg[1];
237 acc_data_next[1] = int_data_reg[2];
238
239 // register 2nd sum
240 int_data_next[1] = acc_data_wire[1];
241
242 int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]};
243
244 int_case_next = 3'd5;
245 end
246 5: // 3rd sum
247 begin
248 int_flag_next = 1'b1;
249
250 int_addr_next = {2'd3, int_lfsr_reg[4:1]};
251
252 // set read addr for 1st pipeline
253 int_chan_next = 2'd0;
254
255 // prepare registers for 4th sum
256 acc_data_next[0] = int_data_reg[2];
257 acc_data_next[1] = int_data_reg[3];
258
259 // register 3rd sum
260 int_data_next[2] = acc_data_wire[1];
261
262 // register 4th output
263 int_data_next[4] = int_data_reg[3];
264
265 int_case_next = 3'd2;
266 end
267 default:
268 begin
269 int_case_next = 3'd0;
270 end
271 endcase
272 end
273
274 assign out_data = int_data_reg[4];
275
276endmodule
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