source: sandbox/MultiChannelUSB/deconv.v@ 132

Last change on this file since 132 was 130, checked in by demin, 14 years ago

add 4th stage
File size: 12.0 KB
Line 
1module deconv
2 #(
3 parameter size = 1, // number of channels
4 parameter shift = 24, // right shift of the result
5 parameter width = 27, // bit width of the input data
6 parameter widthr = 12 // bit width of the output data
7 )
8 (
9 input wire clock, frame, reset,
10 input wire [4*size*6-1:0] del_data,
11 input wire [4*size*6-1:0] amp_data,
12 input wire [4*size*16-1:0] tau_data,
13 input wire [4*size*width-1:0] inp_data,
14 output wire [4*size*widthr-1:0] out_data
15 );
16
17 localparam width1 = width + 1;
18 localparam width2 = width + 6 + 1;
19 localparam width3 = width + 16 + 3;
20
21 reg int_wren_reg, int_wren_next;
22 reg int_flag_reg, int_flag_next;
23 reg [1:0] int_chan_reg, int_chan_next;
24 reg [2:0] int_case_reg, int_case_next;
25 reg [7:0] int_addr_reg, int_addr_next;
26
27 reg [5:0] del_addr_reg, del_addr_next;
28 wire [5:0] del_addr_wire;
29 wire [7:0] int_addr_wire;
30
31 reg [size*widthr-1:0] out_data_reg [4:0], out_data_next [4:0];
32 wire [size*widthr-1:0] out_data_wire;
33
34 wire [size*width3-1:0] add_data_wire;
35
36 wire [size*width3-1:0] mul_data_wire [1:0];
37
38 reg [size*width2-1:0] acc_data_reg [4:0], acc_data_next [4:0];
39 wire [size*width2-1:0] acc_data_wire;
40
41 wire [size*width1-1:0] sub_data_wire;
42
43 reg [size*width-1:0] inp_data_reg [3:0], inp_data_next [3:0];
44 wire [size*width-1:0] inp_data_wire [4:0];
45
46 reg [size*6-1:0] amp_data_reg, amp_data_next;
47 wire [size*6-1:0] amp_data_wire [3:0];
48
49 reg [size*16-1:0] tau_data_reg, tau_data_next;
50 wire [size*16-1:0] tau_data_wire [3:0];
51
52 integer i;
53 genvar j;
54
55 generate
56 for (j = 0; j < size; j = j + 1)
57 begin : INT_DATA
58 assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(4*j+0)*width+width-1:(4*j+0)*width];
59 assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(4*j+1)*width+width-1:(4*j+1)*width];
60 assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(4*j+2)*width+width-1:(4*j+2)*width];
61 assign inp_data_wire[3][j*width+width-1:j*width] = inp_data[(4*j+3)*width+width-1:(4*j+3)*width];
62 assign amp_data_wire[0][j*6+6-1:j*6] = amp_data[(4*j+0)*6+6-1:(4*j+0)*6];
63 assign amp_data_wire[1][j*6+6-1:j*6] = amp_data[(4*j+1)*6+6-1:(4*j+1)*6];
64 assign amp_data_wire[2][j*6+6-1:j*6] = amp_data[(4*j+2)*6+6-1:(4*j+2)*6];
65 assign amp_data_wire[3][j*6+6-1:j*6] = amp_data[(4*j+3)*6+6-1:(4*j+3)*6];
66 assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(4*j+0)*16+16-1:(4*j+0)*16];
67 assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(4*j+1)*16+16-1:(4*j+1)*16];
68 assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(4*j+2)*16+16-1:(4*j+2)*16];
69 assign tau_data_wire[3][j*16+16-1:j*16] = tau_data[(4*j+3)*16+16-1:(4*j+3)*16];
70
71 lpm_mux #(
72 .lpm_size(4),
73 .lpm_type("LPM_MUX"),
74 .lpm_width(8),
75 .lpm_widths(2)) mux_unit_1 (
76 .sel(int_chan_next),
77 .data({
78 2'd3, del_data[(4*j+3)*6+6-1:(4*j+3)*6],
79 2'd2, del_data[(4*j+2)*6+6-1:(4*j+2)*6],
80 2'd1, del_data[(4*j+1)*6+6-1:(4*j+1)*6],
81 2'd0, del_data[(4*j+0)*6+6-1:(4*j+0)*6]}),
82 .result(int_addr_wire));
83
84 lpm_add_sub #(
85 .lpm_direction("SUB"),
86 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
87 .lpm_representation("UNSIGNED"),
88 .lpm_type("LPM_ADD_SUB"),
89 .lpm_width(6)) add_unit_1 (
90 .dataa(del_addr_reg),
91 .datab(int_addr_wire[5:0]),
92 .result(del_addr_wire));
93
94 lpm_add_sub #(
95 .lpm_direction("SUB"),
96 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
97 .lpm_representation("SIGNED"),
98 .lpm_type("LPM_ADD_SUB"),
99 .lpm_width(width1)) sub_unit_1 (
100 .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}),
101 .datab({{(width1-width){1'b0}}, inp_data_wire[4][j*width+width-1:j*width]}),
102 .result(sub_data_wire[j*width1+width1-1:j*width1]));
103
104 lpm_add_sub #(
105 .lpm_direction("ADD"),
106 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
107 .lpm_representation("SIGNED"),
108 .lpm_type("LPM_ADD_SUB"),
109 .lpm_width(width2)) acc_unit_1 (
110 .dataa({{(width2-width1+1){sub_data_wire[j*width1+width1-1]}}, sub_data_wire[j*width1+width1-2:j*width1]}),
111 .datab(acc_data_reg[0][j*width2+width2-1:j*width2]),
112 .result(acc_data_wire[j*width2+width2-1:j*width2]));
113
114 lpm_mult #(
115 .lpm_hint("MAXIMIZE_SPEED=9"),
116 .lpm_representation("SIGNED"),
117 .lpm_type("LPM_MULT"),
118 .lpm_pipeline(4),
119 .lpm_widtha(width1),
120 .lpm_widthb(17),
121 .lpm_widthp(width3)) mult_unit_1 (
122 .clock(clock),
123 .clken(int_wren_reg),
124 .dataa(sub_data_wire[j*width1+width1-1:j*width1]),
125 .datab({1'b0, tau_data_reg[j*16+16-1:j*16]}),
126 .result(mul_data_wire[0][j*width3+width3-1:j*width3]));
127
128 lpm_mult #(
129 .lpm_hint("MAXIMIZE_SPEED=9"),
130 .lpm_representation("UNSIGNED"),
131 .lpm_type("LPM_MULT"),
132 .lpm_pipeline(4),
133 .lpm_widtha(width2),
134 .lpm_widthb(6),
135 .lpm_widthp(width3)) mult_unit_2 (
136 .clock(clock),
137 .clken(int_wren_reg),
138 .dataa(acc_data_reg[0][j*width2+width2-1:j*width2]),
139 .datab(amp_data_reg[j*6+6-1:j*6]),
140 .result(mul_data_wire[1][j*width3+width3-1:j*width3]));
141
142 lpm_add_sub #(
143 .lpm_direction("ADD"),
144 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
145 .lpm_representation("SIGNED"),
146 .lpm_type("LPM_ADD_SUB"),
147 .lpm_width(width3)) add_unit_2 (
148 .dataa(mul_data_wire[0][j*width3+width3-1:j*width3]),
149 .datab(mul_data_wire[1][j*width3+width3-1:j*width3]),
150 .result(add_data_wire[j*width3+width3-1:j*width3]));
151
152
153 lpm_add_sub #(
154 .lpm_direction("ADD"),
155 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
156 .lpm_representation("UNSIGNED"),
157 .lpm_type("LPM_ADD_SUB"),
158 .lpm_width(widthr)) add_unit_3 (
159 .dataa(add_data_wire[j*width3+shift+widthr-1:j*width3+shift]),
160 .datab({{(widthr-1){1'b0}}, add_data_wire[j*width3+shift-1]}),
161 .result(out_data_wire[j*widthr+widthr-1:j*widthr]));
162
163 end
164 endgenerate
165
166
167 altsyncram #(
168 .address_aclr_b("NONE"),
169 .address_reg_b("CLOCK0"),
170 .clock_enable_input_a("BYPASS"),
171 .clock_enable_input_b("BYPASS"),
172 .clock_enable_output_b("BYPASS"),
173 .intended_device_family("Cyclone III"),
174 .lpm_type("altsyncram"),
175 .numwords_a(256),
176 .numwords_b(256),
177 .operation_mode("DUAL_PORT"),
178 .outdata_aclr_b("NONE"),
179 .outdata_reg_b("CLOCK0"),
180 .power_up_uninitialized("FALSE"),
181 .read_during_write_mode_mixed_ports("DONT_CARE"),
182 .widthad_a(8),
183 .widthad_b(8),
184 .width_a(size*width),
185 .width_b(size*width),
186 .width_byteena_a(1)) ram_unit_1 (
187 .wren_a(int_wren_reg),
188 .clock0(clock),
189 .address_a(int_addr_reg),
190 .address_b({int_addr_wire[7:6], del_addr_wire}),
191 .data_a(inp_data_reg[0]),
192 .q_b(inp_data_wire[4]),
193 .aclr0(1'b0),
194 .aclr1(1'b0),
195 .addressstall_a(1'b0),
196 .addressstall_b(1'b0),
197 .byteena_a(1'b1),
198 .byteena_b(1'b1),
199 .clock1(1'b1),
200 .clocken0(1'b1),
201 .clocken1(1'b1),
202 .clocken2(1'b1),
203 .clocken3(1'b1),
204 .data_b({(size*width){1'b1}}),
205 .eccstatus(),
206 .q_a(),
207 .rden_a(1'b1),
208 .rden_b(1'b1),
209 .wren_b(1'b0));
210
211 always @(posedge clock)
212 begin
213 if (reset)
214 begin
215 int_wren_reg <= 1'b1;
216 int_flag_reg <= 1'b0;
217 int_chan_reg <= 2'd0;
218 int_case_reg <= 3'd0;
219 del_addr_reg <= 6'd0;
220 int_addr_reg <= 8'd0;
221 amp_data_reg <= 6'd0;
222 tau_data_reg <= 16'd0;
223 for(i = 0; i <= 3; i = i + 1)
224 begin
225 inp_data_reg[i] <= {(size*width){1'b0}};
226 end
227 for(i = 0; i <= 4; i = i + 1)
228 begin
229 acc_data_reg[i] <= {(size*width2){1'b0}};
230 out_data_reg[i] <= {(size*widthr){1'b0}};
231 end
232 end
233 else
234 begin
235 int_wren_reg <= int_wren_next;
236 int_flag_reg <= int_flag_next;
237 int_chan_reg <= int_chan_next;
238 int_case_reg <= int_case_next;
239 del_addr_reg <= del_addr_next;
240 int_addr_reg <= int_addr_next;
241 amp_data_reg <= amp_data_next;
242 tau_data_reg <= tau_data_next;
243 for(i = 0; i <= 3; i = i + 1)
244 begin
245 inp_data_reg[i] <= inp_data_next[i];
246 end
247 for(i = 0; i <= 4; i = i + 1)
248 begin
249 acc_data_reg[i] <= acc_data_next[i];
250 out_data_reg[i] <= out_data_next[i];
251 end
252 end
253 end
254
255 always @*
256 begin
257 int_wren_next = int_wren_reg;
258 int_flag_next = int_flag_reg;
259 int_chan_next = int_chan_reg;
260 int_case_next = int_case_reg;
261 del_addr_next = del_addr_reg;
262 int_addr_next = int_addr_reg;
263 amp_data_next = amp_data_reg;
264 tau_data_next = tau_data_reg;
265 for(i = 0; i <= 3; i = i + 1)
266 begin
267 inp_data_next[i] = inp_data_reg[i];
268 end
269 for(i = 0; i <= 4; i = i + 1)
270 begin
271 acc_data_next[i] = acc_data_reg[i];
272 out_data_next[i] = out_data_reg[i];
273 end
274
275 case (int_case_reg)
276 0:
277 begin
278 // write zeros
279 int_wren_next = 1'b1;
280 del_addr_next = 6'd0;
281 int_addr_next = 8'd0;
282 amp_data_next = 6'd0;
283 tau_data_next = 16'd0;
284 for(i = 0; i <= 3; i = i + 1)
285 begin
286 inp_data_next[i] = {(size*width){1'b0}};
287 end
288 for(i = 0; i <= 4; i = i + 1)
289 begin
290 acc_data_next[i] = {(size*width2){1'b0}};
291 out_data_next[i] = {(size*widthr){1'b0}};
292 end
293
294 int_case_next = 3'd1;
295 end
296 1:
297 begin
298 // write zeros
299 int_addr_next = int_addr_reg + 8'd1;
300 if (&int_addr_reg)
301 begin
302 int_wren_next = 1'b0;
303 int_flag_next = 1'b0;
304 int_chan_next = 2'd0;
305 int_case_next = 3'd2;
306 end
307 end
308 2: // frame
309 begin
310 int_flag_next = 1'b0;
311 int_wren_next = frame;
312 if (frame)
313 begin
314 int_addr_next[7:6] = 2'd0;
315
316 // set read addr for 2nd pipeline
317 int_chan_next = 2'd1;
318
319 // register input data for 2nd, 3rd and 4th sums
320 inp_data_next[1] = inp_data_wire[1];
321 inp_data_next[2] = inp_data_wire[2];
322 inp_data_next[3] = inp_data_wire[3];
323
324 // prepare registers for 1st sum
325 inp_data_next[0] = inp_data_wire[0];
326 acc_data_next[0] = acc_data_reg[1];
327
328 tau_data_next = tau_data_wire[0];
329 amp_data_next = amp_data_wire[0];
330
331 int_case_next = 3'd3;
332 end
333 if (int_flag_reg) // register 4th sum
334 begin
335 int_addr_next[5:0] = del_addr_reg;
336 // register 4th sum
337 acc_data_next[4] = acc_data_wire;
338 out_data_next[3] = out_data_wire;
339 end
340 end
341 3: // 1st sum
342 begin
343 int_addr_next[7:6] = 2'd1;
344
345 // set read addr for 3rd pipeline
346 int_chan_next = 2'd2;
347
348 // prepare registers for 2nd sum
349 inp_data_next[0] = inp_data_reg[1];
350 acc_data_next[0] = acc_data_reg[2];
351
352 tau_data_next = tau_data_wire[1];
353 amp_data_next = amp_data_wire[1];
354
355 // register 1st sum
356 acc_data_next[1] = acc_data_wire;
357 out_data_next[0] = out_data_wire;
358
359 int_case_next = 3'd4;
360 end
361 4: // 2nd sum
362 begin
363 int_addr_next[7:6] = 2'd2;
364
365 // set read addr for 4th pipeline
366 int_chan_next = 2'd3;
367
368 // prepare registers for 3rd sum
369 inp_data_next[0] = inp_data_reg[2];
370 acc_data_next[0] = acc_data_reg[3];
371
372 tau_data_next = tau_data_wire[2];
373 amp_data_next = amp_data_wire[2];
374
375 // register 2nd sum
376 acc_data_next[2] = acc_data_wire;
377 out_data_next[1] = out_data_wire;
378
379 del_addr_next = del_addr_reg + 6'd1;
380
381 int_case_next = 3'd5;
382 end
383 5: // 3rd sum
384 begin
385 int_flag_next = 1'b1;
386
387 int_addr_next[7:6] = 2'd3;
388
389 // set read addr for 1st pipeline
390 int_chan_next = 2'd0;
391
392 // prepare registers for 4th sum
393 inp_data_next[0] = inp_data_reg[3];
394 acc_data_next[0] = acc_data_reg[4];
395
396 tau_data_next = tau_data_wire[3];
397 amp_data_next = amp_data_wire[3];
398
399 // register 3rd sum
400 acc_data_next[3] = acc_data_wire;
401 out_data_next[2] = out_data_wire;
402
403 // register 4th output
404 out_data_next[4] = out_data_next[3];
405
406 int_case_next = 3'd2;
407 end
408 default:
409 begin
410 int_case_next = 3'd0;
411 end
412 endcase
413 end
414
415 assign out_data = {out_data_next[4], out_data_reg[2], out_data_reg[1], out_data_reg[0]};
416
417endmodule
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