| 1 | module deconv
|
|---|
| 2 | #(
|
|---|
| 3 | parameter shift = 24, // right shift of the result
|
|---|
| 4 | parameter width = 27, // bit width of the input data
|
|---|
| 5 | parameter widthr = 12 // bit width of the output data
|
|---|
| 6 | )
|
|---|
| 7 | (
|
|---|
| 8 | input wire clock, frame, reset,
|
|---|
| 9 | input wire [4*6-1:0] del_data,
|
|---|
| 10 | input wire [4*6-1:0] amp_data,
|
|---|
| 11 | input wire [4*16-1:0] tau_data,
|
|---|
| 12 | input wire [4*width-1:0] inp_data,
|
|---|
| 13 | output wire [4*widthr-1:0] out_data
|
|---|
| 14 | );
|
|---|
| 15 |
|
|---|
| 16 | localparam width1 = width + 1;
|
|---|
| 17 | localparam width2 = width + 6 + 1;
|
|---|
| 18 | localparam width3 = width + 16 + 3;
|
|---|
| 19 |
|
|---|
| 20 | reg int_wren_reg, int_wren_next;
|
|---|
| 21 | reg int_flag_reg, int_flag_next;
|
|---|
| 22 | reg [1:0] int_chan_reg, int_chan_next;
|
|---|
| 23 | reg [2:0] int_case_reg, int_case_next;
|
|---|
| 24 | reg [7:0] int_addr_reg, int_addr_next;
|
|---|
| 25 |
|
|---|
| 26 | reg [5:0] del_addr_reg, del_addr_next;
|
|---|
| 27 | wire [5:0] del_addr_wire;
|
|---|
| 28 | wire [7:0] int_addr_wire;
|
|---|
| 29 |
|
|---|
| 30 | reg [widthr-1:0] out_data_reg [4:0], out_data_next [4:0];
|
|---|
| 31 | wire [widthr-1:0] out_data_wire;
|
|---|
| 32 |
|
|---|
| 33 | wire [width3-1:0] add_data_wire;
|
|---|
| 34 |
|
|---|
| 35 | wire [width3-1:0] mul_data_wire [1:0];
|
|---|
| 36 |
|
|---|
| 37 | reg [width2-1:0] acc_data_reg [4:0], acc_data_next [4:0];
|
|---|
| 38 | wire [width2-1:0] acc_data_wire;
|
|---|
| 39 |
|
|---|
| 40 | wire [width1-1:0] sub_data_wire;
|
|---|
| 41 |
|
|---|
| 42 | reg [width-1:0] inp_data_reg [3:0], inp_data_next [3:0];
|
|---|
| 43 | wire [width-1:0] inp_data_wire [4:0];
|
|---|
| 44 |
|
|---|
| 45 | reg [5:0] amp_data_reg, amp_data_next;
|
|---|
| 46 | wire [5:0] amp_data_wire [3:0];
|
|---|
| 47 |
|
|---|
| 48 | reg [15:0] tau_data_reg, tau_data_next;
|
|---|
| 49 | wire [15:0] tau_data_wire [3:0];
|
|---|
| 50 |
|
|---|
| 51 | integer i;
|
|---|
| 52 | genvar j;
|
|---|
| 53 |
|
|---|
| 54 | generate
|
|---|
| 55 | for (j = 0; j < 4; j = j + 1)
|
|---|
| 56 | begin : INT_DATA
|
|---|
| 57 | assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
|
|---|
| 58 | assign amp_data_wire[j] = amp_data[j*6+6-1:j*6];
|
|---|
| 59 | assign tau_data_wire[j] = tau_data[j*16+16-1:j*16];
|
|---|
| 60 | end
|
|---|
| 61 | endgenerate
|
|---|
| 62 |
|
|---|
| 63 | lpm_mux #(
|
|---|
| 64 | .lpm_size(4),
|
|---|
| 65 | .lpm_type("LPM_MUX"),
|
|---|
| 66 | .lpm_width(8),
|
|---|
| 67 | .lpm_widths(2)) mux_unit_1 (
|
|---|
| 68 | .sel(int_chan_next),
|
|---|
| 69 | .data({
|
|---|
| 70 | 2'd3, del_data[3*6+6-1:3*6],
|
|---|
| 71 | 2'd2, del_data[2*6+6-1:2*6],
|
|---|
| 72 | 2'd1, del_data[1*6+6-1:1*6],
|
|---|
| 73 | 2'd0, del_data[0*6+6-1:0*6]}),
|
|---|
| 74 | .result(int_addr_wire));
|
|---|
| 75 |
|
|---|
| 76 | assign del_addr_wire = del_addr_reg - int_addr_wire[5:0];
|
|---|
| 77 |
|
|---|
| 78 | assign sub_data_wire =
|
|---|
| 79 | {{(width1-width){1'b0}}, inp_data_reg[0]}
|
|---|
| 80 | - {{(width1-width){1'b0}}, inp_data_wire[4]};
|
|---|
| 81 |
|
|---|
| 82 | assign acc_data_wire =
|
|---|
| 83 | {{(width2-width1+1){sub_data_wire[width1-1]}}, sub_data_wire[width1-2:0]}
|
|---|
| 84 | + acc_data_reg[0];
|
|---|
| 85 |
|
|---|
| 86 | lpm_mult #(
|
|---|
| 87 | .lpm_hint("MAXIMIZE_SPEED=9"),
|
|---|
| 88 | .lpm_representation("SIGNED"),
|
|---|
| 89 | .lpm_type("LPM_MULT"),
|
|---|
| 90 | .lpm_pipeline(3),
|
|---|
| 91 | .lpm_widtha(width1),
|
|---|
| 92 | .lpm_widthb(17),
|
|---|
| 93 | .lpm_widthp(width3)) mult_unit_1 (
|
|---|
| 94 | .clock(clock),
|
|---|
| 95 | .clken(int_wren_reg),
|
|---|
| 96 | .dataa(sub_data_wire),
|
|---|
| 97 | .datab({1'b0, tau_data_reg}),
|
|---|
| 98 | .result(mul_data_wire[0]));
|
|---|
| 99 |
|
|---|
| 100 | lpm_mult #(
|
|---|
| 101 | .lpm_hint("MAXIMIZE_SPEED=9"),
|
|---|
| 102 | .lpm_representation("UNSIGNED"),
|
|---|
| 103 | .lpm_type("LPM_MULT"),
|
|---|
| 104 | .lpm_pipeline(3),
|
|---|
| 105 | .lpm_widtha(width2),
|
|---|
| 106 | .lpm_widthb(6),
|
|---|
| 107 | .lpm_widthp(width3)) mult_unit_2 (
|
|---|
| 108 | .clock(clock),
|
|---|
| 109 | .clken(int_wren_reg),
|
|---|
| 110 | .dataa(acc_data_reg[0]),
|
|---|
| 111 | .datab(amp_data_reg),
|
|---|
| 112 | .result(mul_data_wire[1]));
|
|---|
| 113 |
|
|---|
| 114 | assign add_data_wire =
|
|---|
| 115 | mul_data_wire[0]
|
|---|
| 116 | + mul_data_wire[1];
|
|---|
| 117 |
|
|---|
| 118 | assign out_data_wire =
|
|---|
| 119 | add_data_wire[shift+widthr-1:shift]
|
|---|
| 120 | + {{(widthr-1){add_data_wire[width3-1]}}, add_data_wire[shift-1]};
|
|---|
| 121 |
|
|---|
| 122 | altsyncram #(
|
|---|
| 123 | .address_aclr_b("NONE"),
|
|---|
| 124 | .address_reg_b("CLOCK0"),
|
|---|
| 125 | .clock_enable_input_a("BYPASS"),
|
|---|
| 126 | .clock_enable_input_b("BYPASS"),
|
|---|
| 127 | .clock_enable_output_b("BYPASS"),
|
|---|
| 128 | .intended_device_family("Cyclone III"),
|
|---|
| 129 | .lpm_type("altsyncram"),
|
|---|
| 130 | .numwords_a(256),
|
|---|
| 131 | .numwords_b(256),
|
|---|
| 132 | .operation_mode("DUAL_PORT"),
|
|---|
| 133 | .outdata_aclr_b("NONE"),
|
|---|
| 134 | .outdata_reg_b("CLOCK0"),
|
|---|
| 135 | .power_up_uninitialized("FALSE"),
|
|---|
| 136 | .read_during_write_mode_mixed_ports("DONT_CARE"),
|
|---|
| 137 | .widthad_a(8),
|
|---|
| 138 | .widthad_b(8),
|
|---|
| 139 | .width_a(width),
|
|---|
| 140 | .width_b(width),
|
|---|
| 141 | .width_byteena_a(1)) ram_unit_1 (
|
|---|
| 142 | .wren_a(int_wren_reg),
|
|---|
| 143 | .clock0(clock),
|
|---|
| 144 | .address_a(int_addr_reg),
|
|---|
| 145 | .address_b({int_addr_wire[7:6], del_addr_wire}),
|
|---|
| 146 | .data_a(inp_data_reg[0]),
|
|---|
| 147 | .q_b(inp_data_wire[4]),
|
|---|
| 148 | .aclr0(1'b0),
|
|---|
| 149 | .aclr1(1'b0),
|
|---|
| 150 | .addressstall_a(1'b0),
|
|---|
| 151 | .addressstall_b(1'b0),
|
|---|
| 152 | .byteena_a(1'b1),
|
|---|
| 153 | .byteena_b(1'b1),
|
|---|
| 154 | .clock1(1'b1),
|
|---|
| 155 | .clocken0(1'b1),
|
|---|
| 156 | .clocken1(1'b1),
|
|---|
| 157 | .clocken2(1'b1),
|
|---|
| 158 | .clocken3(1'b1),
|
|---|
| 159 | .data_b({(width){1'b1}}),
|
|---|
| 160 | .eccstatus(),
|
|---|
| 161 | .q_a(),
|
|---|
| 162 | .rden_a(1'b1),
|
|---|
| 163 | .rden_b(1'b1),
|
|---|
| 164 | .wren_b(1'b0));
|
|---|
| 165 |
|
|---|
| 166 | always @(posedge clock)
|
|---|
| 167 | begin
|
|---|
| 168 | if (reset)
|
|---|
| 169 | begin
|
|---|
| 170 | int_wren_reg <= 1'b1;
|
|---|
| 171 | int_flag_reg <= 1'b0;
|
|---|
| 172 | int_chan_reg <= 2'd0;
|
|---|
| 173 | int_case_reg <= 3'd0;
|
|---|
| 174 | del_addr_reg <= 6'd0;
|
|---|
| 175 | int_addr_reg <= 8'd0;
|
|---|
| 176 | amp_data_reg <= 6'd0;
|
|---|
| 177 | tau_data_reg <= 16'd0;
|
|---|
| 178 | for(i = 0; i <= 3; i = i + 1)
|
|---|
| 179 | begin
|
|---|
| 180 | inp_data_reg[i] <= {(width){1'b0}};
|
|---|
| 181 | end
|
|---|
| 182 | for(i = 0; i <= 4; i = i + 1)
|
|---|
| 183 | begin
|
|---|
| 184 | acc_data_reg[i] <= {(width2){1'b0}};
|
|---|
| 185 | out_data_reg[i] <= {(widthr){1'b0}};
|
|---|
| 186 | end
|
|---|
| 187 | end
|
|---|
| 188 | else
|
|---|
| 189 | begin
|
|---|
| 190 | int_wren_reg <= int_wren_next;
|
|---|
| 191 | int_flag_reg <= int_flag_next;
|
|---|
| 192 | int_chan_reg <= int_chan_next;
|
|---|
| 193 | int_case_reg <= int_case_next;
|
|---|
| 194 | del_addr_reg <= del_addr_next;
|
|---|
| 195 | int_addr_reg <= int_addr_next;
|
|---|
| 196 | amp_data_reg <= amp_data_next;
|
|---|
| 197 | tau_data_reg <= tau_data_next;
|
|---|
| 198 | for(i = 0; i <= 3; i = i + 1)
|
|---|
| 199 | begin
|
|---|
| 200 | inp_data_reg[i] <= inp_data_next[i];
|
|---|
| 201 | end
|
|---|
| 202 | for(i = 0; i <= 4; i = i + 1)
|
|---|
| 203 | begin
|
|---|
| 204 | acc_data_reg[i] <= acc_data_next[i];
|
|---|
| 205 | out_data_reg[i] <= out_data_next[i];
|
|---|
| 206 | end
|
|---|
| 207 | end
|
|---|
| 208 | end
|
|---|
| 209 |
|
|---|
| 210 | always @*
|
|---|
| 211 | begin
|
|---|
| 212 | int_wren_next = int_wren_reg;
|
|---|
| 213 | int_flag_next = int_flag_reg;
|
|---|
| 214 | int_chan_next = int_chan_reg;
|
|---|
| 215 | int_case_next = int_case_reg;
|
|---|
| 216 | del_addr_next = del_addr_reg;
|
|---|
| 217 | int_addr_next = int_addr_reg;
|
|---|
| 218 | amp_data_next = amp_data_reg;
|
|---|
| 219 | tau_data_next = tau_data_reg;
|
|---|
| 220 | for(i = 0; i <= 3; i = i + 1)
|
|---|
| 221 | begin
|
|---|
| 222 | inp_data_next[i] = inp_data_reg[i];
|
|---|
| 223 | end
|
|---|
| 224 | for(i = 0; i <= 4; i = i + 1)
|
|---|
| 225 | begin
|
|---|
| 226 | acc_data_next[i] = acc_data_reg[i];
|
|---|
| 227 | out_data_next[i] = out_data_reg[i];
|
|---|
| 228 | end
|
|---|
| 229 |
|
|---|
| 230 | case (int_case_reg)
|
|---|
| 231 | 0:
|
|---|
| 232 | begin
|
|---|
| 233 | // write zeros
|
|---|
| 234 | int_wren_next = 1'b1;
|
|---|
| 235 | del_addr_next = 6'd0;
|
|---|
| 236 | int_addr_next = 8'd0;
|
|---|
| 237 | amp_data_next = 6'd0;
|
|---|
| 238 | tau_data_next = 16'd0;
|
|---|
| 239 | for(i = 0; i <= 3; i = i + 1)
|
|---|
| 240 | begin
|
|---|
| 241 | inp_data_next[i] = {(width){1'b0}};
|
|---|
| 242 | end
|
|---|
| 243 | for(i = 0; i <= 4; i = i + 1)
|
|---|
| 244 | begin
|
|---|
| 245 | acc_data_next[i] = {(width2){1'b0}};
|
|---|
| 246 | out_data_next[i] = {(widthr){1'b0}};
|
|---|
| 247 | end
|
|---|
| 248 |
|
|---|
| 249 | int_case_next = 3'd1;
|
|---|
| 250 | end
|
|---|
| 251 | 1:
|
|---|
| 252 | begin
|
|---|
| 253 | // write zeros
|
|---|
| 254 | int_addr_next = int_addr_reg + 8'd1;
|
|---|
| 255 | if (&int_addr_reg)
|
|---|
| 256 | begin
|
|---|
| 257 | int_wren_next = 1'b0;
|
|---|
| 258 | int_flag_next = 1'b0;
|
|---|
| 259 | int_chan_next = 2'd0;
|
|---|
| 260 | int_case_next = 3'd2;
|
|---|
| 261 | end
|
|---|
| 262 | end
|
|---|
| 263 | 2: // frame
|
|---|
| 264 | begin
|
|---|
| 265 | int_flag_next = 1'b0;
|
|---|
| 266 | int_wren_next = frame;
|
|---|
| 267 | if (frame)
|
|---|
| 268 | begin
|
|---|
| 269 | int_addr_next[7:6] = 2'd0;
|
|---|
| 270 |
|
|---|
| 271 | // set read addr for 2nd pipeline
|
|---|
| 272 | int_chan_next = 2'd1;
|
|---|
| 273 |
|
|---|
| 274 | // register input data for 2nd, 3rd and 4th sums
|
|---|
| 275 | inp_data_next[1] = inp_data_wire[1];
|
|---|
| 276 | inp_data_next[2] = inp_data_wire[2];
|
|---|
| 277 | inp_data_next[3] = inp_data_wire[3];
|
|---|
| 278 |
|
|---|
| 279 | // prepare registers for 1st sum
|
|---|
| 280 | inp_data_next[0] = inp_data_wire[0];
|
|---|
| 281 | acc_data_next[0] = acc_data_reg[1];
|
|---|
| 282 |
|
|---|
| 283 | tau_data_next = tau_data_wire[0];
|
|---|
| 284 | amp_data_next = amp_data_wire[0];
|
|---|
| 285 |
|
|---|
| 286 | int_case_next = 3'd3;
|
|---|
| 287 | end
|
|---|
| 288 | if (int_flag_reg) // register 4th sum
|
|---|
| 289 | begin
|
|---|
| 290 | int_addr_next[5:0] = del_addr_reg;
|
|---|
| 291 | // register 4th sum and 1st product
|
|---|
| 292 | acc_data_next[4] = acc_data_wire;
|
|---|
| 293 | out_data_next[0] = out_data_wire;
|
|---|
| 294 | end
|
|---|
| 295 | end
|
|---|
| 296 | 3: // 1st sum
|
|---|
| 297 | begin
|
|---|
| 298 | int_addr_next[7:6] = 2'd1;
|
|---|
| 299 |
|
|---|
| 300 | // set read addr for 3rd pipeline
|
|---|
| 301 | int_chan_next = 2'd2;
|
|---|
| 302 |
|
|---|
| 303 | // prepare registers for 2nd sum
|
|---|
| 304 | inp_data_next[0] = inp_data_reg[1];
|
|---|
| 305 | acc_data_next[0] = acc_data_reg[2];
|
|---|
| 306 |
|
|---|
| 307 | tau_data_next = tau_data_wire[1];
|
|---|
| 308 | amp_data_next = amp_data_wire[1];
|
|---|
| 309 |
|
|---|
| 310 | // register 1st sum and 2nd product
|
|---|
| 311 | acc_data_next[1] = acc_data_wire;
|
|---|
| 312 | out_data_next[1] = out_data_wire;
|
|---|
| 313 |
|
|---|
| 314 | int_case_next = 3'd4;
|
|---|
| 315 | end
|
|---|
| 316 | 4: // 2nd sum
|
|---|
| 317 | begin
|
|---|
| 318 | int_addr_next[7:6] = 2'd2;
|
|---|
| 319 |
|
|---|
| 320 | // set read addr for 4th pipeline
|
|---|
| 321 | int_chan_next = 2'd3;
|
|---|
| 322 |
|
|---|
| 323 | // prepare registers for 3rd sum
|
|---|
| 324 | inp_data_next[0] = inp_data_reg[2];
|
|---|
| 325 | acc_data_next[0] = acc_data_reg[3];
|
|---|
| 326 |
|
|---|
| 327 | tau_data_next = tau_data_wire[2];
|
|---|
| 328 | amp_data_next = amp_data_wire[2];
|
|---|
| 329 |
|
|---|
| 330 | // register 2nd sum and 3rd product
|
|---|
| 331 | acc_data_next[2] = acc_data_wire;
|
|---|
| 332 | out_data_next[2] = out_data_wire;
|
|---|
| 333 |
|
|---|
| 334 | del_addr_next = del_addr_reg + 6'd1;
|
|---|
| 335 |
|
|---|
| 336 | int_case_next = 3'd5;
|
|---|
| 337 | end
|
|---|
| 338 | 5: // 3rd sum
|
|---|
| 339 | begin
|
|---|
| 340 | int_flag_next = 1'b1;
|
|---|
| 341 |
|
|---|
| 342 | int_addr_next[7:6] = 2'd3;
|
|---|
| 343 |
|
|---|
| 344 | // set read addr for 1st pipeline
|
|---|
| 345 | int_chan_next = 2'd0;
|
|---|
| 346 |
|
|---|
| 347 | // prepare registers for 4th sum
|
|---|
| 348 | inp_data_next[0] = inp_data_reg[3];
|
|---|
| 349 | acc_data_next[0] = acc_data_reg[4];
|
|---|
| 350 |
|
|---|
| 351 | tau_data_next = tau_data_wire[3];
|
|---|
| 352 | amp_data_next = amp_data_wire[3];
|
|---|
| 353 |
|
|---|
| 354 | // register 3rd sum and 4th product
|
|---|
| 355 | acc_data_next[3] = acc_data_wire;
|
|---|
| 356 | out_data_next[3] = out_data_wire;
|
|---|
| 357 |
|
|---|
| 358 | // register 4th output
|
|---|
| 359 | out_data_next[4] = out_data_reg[0];
|
|---|
| 360 |
|
|---|
| 361 | int_case_next = 3'd2;
|
|---|
| 362 | end
|
|---|
| 363 | default:
|
|---|
| 364 | begin
|
|---|
| 365 | int_case_next = 3'd0;
|
|---|
| 366 | end
|
|---|
| 367 | endcase
|
|---|
| 368 | end
|
|---|
| 369 |
|
|---|
| 370 | assign out_data = {out_data_reg[3], out_data_reg[2], out_data_reg[1], out_data_reg[4]};
|
|---|
| 371 |
|
|---|
| 372 | endmodule
|
|---|
