1 | module deconv
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2 | #(
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3 | parameter size = 1, // number of channels
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4 | parameter width = 16 // bit width of the input data
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5 | )
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6 | (
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7 | input wire clock, frame, reset,
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8 | input wire [3*size*6-1:0] del_data,
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9 | input wire [3*size*8-1:0] amp_data,
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10 | input wire [3*size*16-1:0] tau_data,
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11 | input wire [3*size*width-1:0] inp_data,
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12 | output wire [3*size*widthr-1:0] out_data,
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13 | output wire [3*size*width2-1:0] acc_data
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14 | );
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15 |
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16 | localparam width1 = width + 1;
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17 | localparam width2 = width + 6 + 1;
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18 | localparam widthr = width + 16 + 3;
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19 |
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20 | reg int_wren_reg, int_wren_next;
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21 | reg [1:0] int_chan_reg, int_chan_next;
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22 | reg [2:0] int_case_reg, int_case_next;
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23 | reg [7:0] int_addr_reg, int_addr_next;
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24 |
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25 | reg [5:0] del_addr_reg, del_addr_next;
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26 | wire [5:0] del_addr_wire;
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27 | wire [7:0] int_addr_wire;
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28 |
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29 | reg [size*widthr-1:0] out_data_reg [2:0], out_data_next [2:0];
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30 | wire [size*widthr-1:0] out_data_wire;
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31 |
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32 | reg [size*widthr-1:0] mul_data_reg [7:0], mul_data_next [7:0];
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33 | wire [size*widthr-1:0] mul_data_wire [1:0];
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34 |
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35 | reg [size*width2-1:0] acc_data_reg [3:0], acc_data_next [3:0];
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36 | wire [size*width2-1:0] acc_data_wire;
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37 |
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38 | reg [size*width1-1:0] sub_data_reg [3:0], sub_data_next [3:0];
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39 | wire [size*width1-1:0] sub_data_wire;
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40 |
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41 | reg [size*width-1:0] inp_data_reg [2:0], inp_data_next [2:0];
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42 | wire [size*width-1:0] inp_data_wire [3:0];
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43 |
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44 | reg [size*8-1:0] amp_data_reg, amp_data_next;
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45 | wire [size*8-1:0] amp_data_wire [2:0];
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46 |
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47 | reg [size*16-1:0] tau_data_reg, tau_data_next;
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48 | wire [size*16-1:0] tau_data_wire [2:0];
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49 |
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50 | integer i;
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51 | genvar j;
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52 |
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53 | generate
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54 | for (j = 0; j < size; j = j + 1)
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55 | begin : INT_DATA
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56 | assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(3*j+0)*width+width-1:(3*j+0)*width];
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57 | assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(3*j+1)*width+width-1:(3*j+1)*width];
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58 | assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(3*j+2)*width+width-1:(3*j+2)*width];
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59 | assign amp_data_wire[0][j*8+8-1:j*8] = amp_data[(3*j+0)*8+8-1:(3*j+0)*8];
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60 | assign amp_data_wire[1][j*8+8-1:j*8] = amp_data[(3*j+1)*8+8-1:(3*j+1)*8];
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61 | assign amp_data_wire[2][j*8+8-1:j*8] = amp_data[(3*j+2)*8+8-1:(3*j+2)*8];
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62 | assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(3*j+0)*16+16-1:(3*j+0)*16];
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63 | assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(3*j+1)*16+16-1:(3*j+1)*16];
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64 | assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(3*j+2)*16+16-1:(3*j+2)*16];
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65 |
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66 | lpm_mux #(
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67 | .lpm_size(3),
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68 | .lpm_type("LPM_MUX"),
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69 | .lpm_width(8),
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70 | .lpm_widths(2)) mux_unit_1 (
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71 | .sel(int_chan_next),
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72 | .data({
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73 | 2'd2, del_data[(3*j+2)*6+6-1:(3*j+2)*6],
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74 | 2'd1, del_data[(3*j+1)*6+6-1:(3*j+1)*6],
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75 | 2'd0, del_data[(3*j+0)*6+6-1:(3*j+0)*6]}),
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76 | .result(int_addr_wire));
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77 |
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78 | lpm_add_sub #(
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79 | .lpm_direction("SUB"),
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80 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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81 | .lpm_representation("UNSIGNED"),
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82 | .lpm_type("LPM_ADD_SUB"),
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83 | .lpm_width(6)) add_unit_1 (
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84 | .dataa(del_addr_reg),
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85 | .datab(int_addr_wire[5:0]),
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86 | .result(del_addr_wire));
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87 |
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88 | lpm_add_sub #(
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89 | .lpm_direction("SUB"),
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90 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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91 | .lpm_representation("SIGNED"),
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92 | .lpm_type("LPM_ADD_SUB"),
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93 | .lpm_width(width1)) sub_unit_1 (
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94 | .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}),
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95 | .datab({{(width1-width){1'b0}}, inp_data_wire[3][j*width+width-1:j*width]}),
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96 | .result(sub_data_wire[j*width1+width1-1:j*width1]));
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97 |
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98 | lpm_add_sub #(
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99 | .lpm_direction("ADD"),
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100 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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101 | .lpm_representation("SIGNED"),
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102 | .lpm_type("LPM_ADD_SUB"),
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103 | .lpm_width(width2)) acc_unit_1 (
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104 | .dataa({sub_data_reg[0][j*width1+width1-1], {(width2-width1){1'b0}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),
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105 | // .dataa({width2{1'b0}}),
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106 | .datab(acc_data_reg[0][j*width2+width2-1:j*width2]),
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107 | .result(acc_data_wire[j*width2+width2-1:j*width2]));
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108 |
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109 | lpm_mult #(
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110 | .lpm_hint("MAXIMIZE_SPEED=9"),
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111 | .lpm_representation("SIGNED"),
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112 | .lpm_type("LPM_MULT"),
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113 | .lpm_pipeline(3),
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114 | .lpm_widtha(width1),
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115 | .lpm_widthb(17),
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116 | .lpm_widthp(widthr)) mult_unit_1 (
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117 | .clock(clock),
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118 | .clken(int_wren_reg),
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119 | .dataa(sub_data_reg[0][j*width1+width1-1:j*width1]),
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120 | .datab({1'b0, tau_data_reg[j*16+16-1:j*16]}),
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121 | .result(mul_data_wire[0][j*widthr+widthr-1:j*widthr]));
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122 |
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123 | lpm_mult #(
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124 | .lpm_hint("MAXIMIZE_SPEED=9"),
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125 | .lpm_representation("UNSIGNED"),
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126 | .lpm_type("LPM_MULT"),
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127 | .lpm_pipeline(3),
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128 | .lpm_widtha(width2),
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129 | .lpm_widthb(8),
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130 | .lpm_widthp(widthr)) mult_unit_2 (
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131 | .clock(clock),
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132 | .clken(int_wren_reg),
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133 | .dataa(acc_data_reg[0][j*width2+width2-1:j*width2]),
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134 | .datab(amp_data_reg[j*8+8-1:j*8]),
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135 | .result(mul_data_wire[1][j*widthr+widthr-1:j*widthr]));
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136 |
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137 | lpm_add_sub #(
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138 | .lpm_direction("ADD"),
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139 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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140 | .lpm_representation("SIGNED"),
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141 | .lpm_type("LPM_ADD_SUB"),
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142 | .lpm_width(widthr)) add_unit_2 (
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143 | .dataa(mul_data_reg[0][j*widthr+widthr-1:j*widthr]),
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144 | .datab(mul_data_reg[1][j*widthr+widthr-1:j*widthr]),
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145 | .result(out_data_wire[j*widthr+widthr-1:j*widthr]));
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146 |
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147 | end
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148 | endgenerate
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149 |
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150 |
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151 | altsyncram #(
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152 | .address_aclr_b("NONE"),
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153 | .address_reg_b("CLOCK0"),
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154 | .clock_enable_input_a("BYPASS"),
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155 | .clock_enable_input_b("BYPASS"),
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156 | .clock_enable_output_b("BYPASS"),
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157 | .intended_device_family("Cyclone III"),
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158 | .lpm_type("altsyncram"),
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159 | .numwords_a(256),
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160 | .numwords_b(256),
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161 | .operation_mode("DUAL_PORT"),
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162 | .outdata_aclr_b("NONE"),
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163 | .outdata_reg_b("CLOCK0"),
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164 | .power_up_uninitialized("FALSE"),
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165 | .read_during_write_mode_mixed_ports("DONT_CARE"),
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166 | .widthad_a(8),
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167 | .widthad_b(8),
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168 | .width_a(size*width),
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169 | .width_b(size*width),
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170 | .width_byteena_a(1)) ram_unit_1 (
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171 | .wren_a(int_wren_reg),
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172 | .clock0(clock),
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173 | .address_a(int_addr_reg),
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174 | .address_b({int_addr_wire[7:6], del_addr_wire}),
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175 | .data_a(inp_data_reg[0]),
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176 | .q_b(inp_data_wire[3]),
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177 | .aclr0(1'b0),
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178 | .aclr1(1'b0),
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179 | .addressstall_a(1'b0),
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180 | .addressstall_b(1'b0),
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181 | .byteena_a(1'b1),
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182 | .byteena_b(1'b1),
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183 | .clock1(1'b1),
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184 | .clocken0(1'b1),
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185 | .clocken1(1'b1),
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186 | .clocken2(1'b1),
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187 | .clocken3(1'b1),
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188 | .data_b({(size*width){1'b1}}),
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189 | .eccstatus(),
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190 | .q_a(),
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191 | .rden_a(1'b1),
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192 | .rden_b(1'b1),
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193 | .wren_b(1'b0));
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194 |
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195 | always @(posedge clock)
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196 | begin
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197 | if (reset)
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198 | begin
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199 | int_wren_reg <= 1'b1;
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200 | int_chan_reg <= 2'd0;
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201 | int_case_reg <= 3'd0;
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202 | del_addr_reg <= 6'd0;
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203 | int_addr_reg <= 8'd0;
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204 | amp_data_reg <= 8'd0;
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205 | tau_data_reg <= 16'd0;
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206 | for(i = 0; i <= 2; i = i + 1)
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207 | begin
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208 | inp_data_reg[i] <= {(size*width){1'b0}};
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209 | out_data_reg[i] <= {(size*widthr){1'b0}};
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210 | end
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211 | for(i = 0; i <= 3; i = i + 1)
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212 | begin
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213 | sub_data_reg[i] <= {(size*width1){1'b0}};
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214 | acc_data_reg[i] <= {(size*width2){1'b0}};
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215 | end
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216 | for(i = 0; i <= 7; i = i + 1)
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217 | begin
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218 | mul_data_reg[i] <= {(size*widthr){1'b0}};
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219 | end
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220 | end
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221 | else
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222 | begin
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223 | int_wren_reg <= int_wren_next;
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224 | int_chan_reg <= int_chan_next;
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225 | int_case_reg <= int_case_next;
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226 | del_addr_reg <= del_addr_next;
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227 | int_addr_reg <= int_addr_next;
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228 | amp_data_reg <= amp_data_next;
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229 | tau_data_reg <= tau_data_next;
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230 | for(i = 0; i <= 2; i = i + 1)
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231 | begin
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232 | inp_data_reg[i] <= inp_data_next[i];
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233 | out_data_reg[i] <= out_data_next[i];
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234 | end
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235 | for(i = 0; i <= 3; i = i + 1)
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236 | begin
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237 | sub_data_reg[i] <= sub_data_next[i];
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238 | acc_data_reg[i] <= acc_data_next[i];
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239 | end
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240 | for(i = 0; i <= 7; i = i + 1)
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241 | begin
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242 | mul_data_reg[i] <= mul_data_next[i];
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243 | end
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244 | end
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245 | end
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246 |
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247 | always @*
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248 | begin
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249 | int_wren_next = int_wren_reg;
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250 | int_chan_next = int_chan_reg;
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251 | int_case_next = int_case_reg;
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252 | del_addr_next = del_addr_reg;
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253 | int_addr_next = int_addr_reg;
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254 | amp_data_next = amp_data_reg;
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255 | tau_data_next = tau_data_reg;
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256 | for(i = 0; i <= 2; i = i + 1)
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257 | begin
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258 | inp_data_next[i] = inp_data_reg[i];
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259 | out_data_next[i] = out_data_reg[i];
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260 | end
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261 | for(i = 0; i <= 3; i = i + 1)
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262 | begin
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263 | sub_data_next[i] = sub_data_reg[i];
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264 | acc_data_next[i] = acc_data_reg[i];
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265 | end
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266 | for(i = 0; i <= 7; i = i + 1)
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267 | begin
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268 | mul_data_next[i] = mul_data_reg[i];
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269 | end
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270 |
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271 | case (int_case_reg)
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272 | 0:
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273 | begin
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274 | // write zeros
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275 | int_wren_next = 1'b1;
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276 | del_addr_next = 6'd0;
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277 | int_addr_next = 8'd0;
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278 | amp_data_next = 8'd0;
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279 | tau_data_next = 16'd0;
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280 | for(i = 0; i <= 2; i = i + 1)
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281 | begin
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282 | inp_data_next[i] = {(size*width){1'b0}};
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283 | out_data_next[i] = {(size*widthr){1'b0}};
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284 | end
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285 | for(i = 0; i <= 3; i = i + 1)
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286 | begin
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287 | sub_data_next[i] = {(size*width1){1'b0}};
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288 | acc_data_next[i] = {(size*width2){1'b0}};
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289 | end
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290 | for(i = 0; i <= 7; i = i + 1)
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291 | begin
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292 | mul_data_next[i] = {(size*widthr){1'b0}};
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293 | end
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294 |
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295 | int_case_next = 3'd1;
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296 | end
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297 | 1:
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298 | begin
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299 | // write zeros
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300 | int_addr_next = int_addr_reg + 8'd1;
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301 | if (&int_addr_reg)
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302 | begin
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303 | int_wren_next = 1'b0;
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304 | int_chan_next = 2'd0;
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305 | int_case_next = 3'd2;
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306 | end
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307 | end
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308 | 2: // frame
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309 | begin
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310 | if (frame)
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311 | begin
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312 | int_wren_next = 1'b1;
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313 |
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314 | int_addr_next[7:6] = 2'd0;
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315 |
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316 | // set read addr for 2nd pipeline
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317 | int_chan_next = 2'd1;
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318 |
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319 | // register input data for 2nd and 3rd sums
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320 | inp_data_next[1] = inp_data_wire[1];
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321 | inp_data_next[2] = inp_data_wire[2];
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322 |
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323 | // prepare registers for 1st sum
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324 | inp_data_next[0] = inp_data_wire[0];
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325 |
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326 | sub_data_next[0] = sub_data_reg[1];
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327 | acc_data_next[0] = acc_data_reg[1];
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328 |
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329 | mul_data_next[0] = mul_data_reg[2];
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330 | mul_data_next[1] = mul_data_reg[3];
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331 |
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332 | tau_data_next = tau_data_wire[0];
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333 | amp_data_next = amp_data_wire[0];
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334 |
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335 | int_case_next = 3'd3;
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336 | end
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337 |
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338 | end
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339 | 3: // 1st sum
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340 | begin
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341 | int_addr_next[7:6] = 2'd1;
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342 |
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343 | // set read addr for 3rd pipeline
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344 | int_chan_next = 2'd2;
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345 |
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346 | // prepare registers for 2nd sum
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347 | inp_data_next[0] = inp_data_reg[1];
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348 |
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349 | sub_data_next[0] = sub_data_reg[2];
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350 | acc_data_next[0] = acc_data_reg[2];
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351 |
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352 | mul_data_next[0] = mul_data_reg[4];
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353 | mul_data_next[1] = mul_data_reg[5];
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354 |
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355 | tau_data_next = tau_data_wire[1];
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356 | amp_data_next = amp_data_wire[1];
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357 |
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358 | // register 1st sum
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359 | sub_data_next[1] = sub_data_wire;
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360 | acc_data_next[1] = acc_data_wire;
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361 | mul_data_next[2] = mul_data_wire[0];
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362 | mul_data_next[3] = mul_data_wire[1];
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363 | out_data_next[0] = out_data_wire;
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364 |
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365 | int_case_next = 3'd4;
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366 | end
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367 | 4: // 2nd sum
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368 | begin
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369 | int_addr_next[7:6] = 2'd2;
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370 |
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371 | // prepare registers for 3rd sum
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372 | inp_data_next[0] = inp_data_reg[2];
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373 |
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374 | sub_data_next[0] = sub_data_reg[3];
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375 | acc_data_next[0] = acc_data_reg[3];
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376 |
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377 | mul_data_next[0] = mul_data_reg[6];
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378 | mul_data_next[1] = mul_data_reg[7];
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379 |
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380 | tau_data_next = tau_data_wire[2];
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381 | amp_data_next = amp_data_wire[2];
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382 |
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383 | // register 2nd sum
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384 | sub_data_next[2] = sub_data_wire;
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385 | acc_data_next[2] = acc_data_wire;
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386 | mul_data_next[4] = mul_data_wire[0];
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387 | mul_data_next[5] = mul_data_wire[1];
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388 | out_data_next[1] = out_data_wire;
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389 |
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390 | del_addr_next = del_addr_reg + 6'd1;
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391 |
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392 | int_case_next = 3'd5;
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393 | end
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394 | 5: // 3rd sum
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395 | begin
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396 | int_wren_next = 1'b0;
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397 |
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398 | // set read addr for 1st pipeline
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399 | int_chan_next = 2'd0;
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400 |
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401 | // register 3rd sum
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402 | sub_data_next[3] = sub_data_wire;
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403 | acc_data_next[3] = acc_data_wire;
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404 | mul_data_next[6] = mul_data_wire[0];
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405 | mul_data_next[7] = mul_data_wire[1];
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406 | out_data_next[2] = out_data_wire;
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407 |
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408 | int_addr_next[5:0] = del_addr_reg;
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409 |
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410 | int_case_next = 3'd2;
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411 | end
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412 | default:
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413 | begin
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414 | int_case_next = 3'd0;
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415 | end
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416 | endcase
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417 | end
|
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418 |
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419 | assign out_data = {out_data_reg[2], out_data_reg[1], out_data_reg[0]};
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420 | assign acc_data = {acc_data_reg[3], acc_data_reg[2], acc_data_reg[1]};
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421 | // assign acc_data = {17'd0, del_addr_wire, 17'd0, del_addr_wire, 17'd0, del_addr_wire};
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422 |
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423 | endmodule
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