[113] | 1 | module deconv
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| 2 | #(
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| 3 | parameter size = 1, // number of channels
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| 4 | parameter width = 16 // bit width of the input data
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| 5 | )
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| 6 | (
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| 7 | input wire clock, frame, reset,
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| 8 | input wire [14:0] del_data,
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| 9 | input wire [3*size*32-1:0] mul_data,
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| 10 | input wire [3*size*width-1:0] inp_data,
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| 11 | output wire [3*size*widthr-1:0] out_data
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| 12 | );
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| 13 |
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| 14 | localparam width1 = width + 6 + 1;
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| 15 | localparam width2 = width + 6 + 6;
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| 16 | localparam widthr = 2*(width + 8);
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| 17 |
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| 18 | reg int_wren_reg, int_wren_next;
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| 19 | reg [1:0] int_chan_reg, int_chan_next;
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| 20 | reg [2:0] int_case_reg, int_case_next;
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| 21 | reg [7:0] int_addr_reg, int_addr_next;
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| 22 |
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| 23 | wire [7:0] int_addr_wire;
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| 24 | wire [5:0] del_addr_wire;
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| 25 |
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| 26 | reg [size*widthr-1:0] acc_data_reg [6:0], acc_data_next [6:0];
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| 27 | reg [size*widthr-1:0] int_data_reg [17:0], int_data_next [17:0];
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| 28 |
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| 29 | wire [size*widthr-1:0] int_data_wire [8:0];
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| 30 |
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| 31 | wire [size*widthr-1:0] mul_data_wire [5:0];
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| 32 |
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| 33 | integer i;
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| 34 | genvar j;
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| 35 |
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| 36 | generate
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| 37 | for (j = 0; j < size; j = j + 1)
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| 38 | begin : INT_DATA
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| 39 | assign int_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+0)*width+width-1:(3*j+0)*width]};
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| 40 | assign int_data_wire[1][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+1)*width+width-1:(3*j+1)*width]};
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| 41 | assign int_data_wire[2][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+2)*width+width-1:(3*j+2)*width]};
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| 42 | assign mul_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+0)*16+16-1:(3*j+0)*16]};
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| 43 | assign mul_data_wire[1][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+1)*16+16-1:(3*j+1)*16]};
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| 44 | assign mul_data_wire[2][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+2)*16+16-1:(3*j+2)*16]};
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| 45 | assign mul_data_wire[3][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+3)*16+16-1:(3*j+3)*16]};
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| 46 | assign mul_data_wire[4][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+4)*16+16-1:(3*j+4)*16]};
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| 47 | assign mul_data_wire[5][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+5)*16+16-1:(3*j+5)*16]};
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| 48 |
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| 49 | lpm_add_sub #(
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| 50 | .lpm_direction("ADD"),
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| 51 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 52 | .lpm_representation("UNSIGNED"),
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| 53 | .lpm_type("LPM_ADD_SUB"),
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| 54 | .lpm_width(6)) add_unit_1 (
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| 55 | .dataa(int_addr_reg[5:0]),
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| 56 | .datab(int_addr_wire[5:0]),
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| 57 | .result(del_addr_wire));
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| 58 |
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| 59 | lpm_add_sub #(
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| 60 | .lpm_direction("SUB"),
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| 61 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 62 | .lpm_representation("SIGNED"),
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| 63 | .lpm_type("LPM_ADD_SUB"),
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| 64 | .lpm_width(widthr)) sub_unit_1 (
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| 65 | .dataa(acc_data_reg[0][j*widthr+widthr-1:j*widthr]),
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| 66 | .datab(int_data_wire[3][j*widthr+widthr-1:j*widthr]),
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| 67 | .result(int_data_wire[4][j*widthr+widthr-1:j*widthr]));
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| 68 |
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| 69 | lpm_add_sub #(
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| 70 | .lpm_direction("ADD"),
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| 71 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 72 | .lpm_representation("SIGNED"),
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| 73 | .lpm_type("LPM_ADD_SUB"),
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| 74 | .lpm_width(widthr)) acc_unit_1 (
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| 75 | .dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]),
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| 76 | .datab(acc_data_reg[2][j*widthr+widthr-1:j*widthr]),
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| 77 | .result(int_data_wire[5][j*widthr+widthr-1:j*widthr]));
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| 78 |
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| 79 | lpm_mult #(
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| 80 | .lpm_hint("MAXIMIZE_SPEED=9"),
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| 81 | .lpm_representation("SIGNED"),
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| 82 | .lpm_type("LPM_MULT"),
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| 83 | .lpm_pipeline(3),
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| 84 | .lpm_widtha(18),
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| 85 | .lpm_widthb(18),
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| 86 | .lpm_widthp(36)) mult_unit_1 (
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| 87 | .clock(clock),
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| 88 | .clken(int_wren_reg),
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| 89 | // .dataa(int_data_wire[4][j*widthr+widthr-1:j*widthr]),
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| 90 | .dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]),
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| 91 | .datab(acc_data_reg[5][j*widthr+widthr-1:j*widthr]),
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| 92 | .result(int_data_wire[6][j*widthr+widthr-1:j*widthr]));
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| 93 |
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| 94 | lpm_mult #(
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| 95 | .lpm_hint("MAXIMIZE_SPEED=9"),
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| 96 | .lpm_representation("SIGNED"),
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| 97 | .lpm_type("LPM_MULT"),
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| 98 | .lpm_pipeline(3),
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| 99 | .lpm_widtha(widthr),
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| 100 | .lpm_widthb(widthr),
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| 101 | .lpm_widthp(widthr)) mult_unit_2 (
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| 102 | .clock(clock),
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| 103 | .clken(int_wren_reg),
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| 104 | // .dataa(int_data_wire[5][j*widthr+widthr-1:j*widthr]),
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| 105 | .dataa(acc_data_reg[2][j*widthr+widthr-1:j*widthr]),
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| 106 | .datab(acc_data_reg[6][j*widthr+widthr-1:j*widthr]),
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| 107 | .result(int_data_wire[7][j*widthr+widthr-1:j*widthr]));
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| 108 |
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| 109 | lpm_add_sub #(
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| 110 | .lpm_direction("ADD"),
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| 111 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 112 | .lpm_representation("SIGNED"),
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| 113 | .lpm_type("LPM_ADD_SUB"),
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| 114 | .lpm_width(widthr)) add_unit_2 (
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| 115 | .dataa(acc_data_reg[3][j*widthr+widthr-1:j*widthr]),
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| 116 | .datab(acc_data_reg[4][j*widthr+widthr-1:j*widthr]),
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| 117 | .result(int_data_wire[8][j*widthr+widthr-1:j*widthr]));
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| 118 |
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| 119 | end
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| 120 | endgenerate
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| 121 |
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| 122 |
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| 123 | altsyncram #(
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| 124 | .address_aclr_b("NONE"),
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| 125 | .address_reg_b("CLOCK0"),
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| 126 | .clock_enable_input_a("BYPASS"),
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| 127 | .clock_enable_input_b("BYPASS"),
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| 128 | .clock_enable_output_b("BYPASS"),
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| 129 | .intended_device_family("Cyclone III"),
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| 130 | .lpm_type("altsyncram"),
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| 131 | .numwords_a(256),
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| 132 | .numwords_b(256),
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| 133 | .operation_mode("DUAL_PORT"),
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| 134 | .outdata_aclr_b("NONE"),
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| 135 | .outdata_reg_b("CLOCK0"),
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| 136 | .power_up_uninitialized("FALSE"),
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| 137 | .read_during_write_mode_mixed_ports("DONT_CARE"),
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| 138 | .widthad_a(8),
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| 139 | .widthad_b(8),
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| 140 | .width_a(size*widthr),
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| 141 | .width_b(size*widthr),
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| 142 | .width_byteena_a(1)) ram_unit_1 (
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| 143 | .wren_a(int_wren_reg),
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| 144 | .clock0(clock),
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| 145 | .address_a(int_addr_reg),
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| 146 | .address_b({int_addr_wire[7:6], del_addr_wire}),
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| 147 | .data_a(acc_data_reg[0]),
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| 148 | .q_b(int_data_wire[3]),
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| 149 | .aclr0(1'b0),
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| 150 | .aclr1(1'b0),
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| 151 | .addressstall_a(1'b0),
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| 152 | .addressstall_b(1'b0),
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| 153 | .byteena_a(1'b1),
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| 154 | .byteena_b(1'b1),
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| 155 | .clock1(1'b1),
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| 156 | .clocken0(1'b1),
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| 157 | .clocken1(1'b1),
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| 158 | .clocken2(1'b1),
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| 159 | .clocken3(1'b1),
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| 160 | .data_b({widthr{1'b1}}),
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| 161 | .eccstatus(),
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| 162 | .q_a(),
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| 163 | .rden_a(1'b1),
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| 164 | .rden_b(1'b1),
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| 165 | .wren_b(1'b0));
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| 166 |
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| 167 | lpm_mux #(
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| 168 | .lpm_size(3),
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| 169 | .lpm_type("LPM_MUX"),
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| 170 | .lpm_width(8),
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| 171 | .lpm_widths(2)) mux_unit_1 (
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| 172 | .sel(int_chan_next),
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| 173 | .data({
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| 174 | 2'd2, 1'b0, del_data[14:10],
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| 175 | 2'd1, 1'b0, del_data[9:5],
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| 176 | 2'd0, 1'b0, del_data[4:0]}),
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| 177 | .result(int_addr_wire));
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| 178 |
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| 179 | always @(posedge clock)
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| 180 | begin
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| 181 | if (reset)
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| 182 | begin
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| 183 | int_wren_reg <= 1'b1;
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| 184 | int_chan_reg <= 2'd0;
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| 185 | int_case_reg <= 3'd0;
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| 186 | int_addr_reg <= 8'd0;
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| 187 | for(i = 0; i <= 6; i = i + 1)
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| 188 | begin
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| 189 | acc_data_reg[i] <= {(size*widthr){1'b0}};
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| 190 | end
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| 191 | for(i = 0; i <= 17; i = i + 1)
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| 192 | begin
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| 193 | int_data_reg[i] <= {(size*widthr){1'b0}};
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| 194 | end
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| 195 | end
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| 196 | else
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| 197 | begin
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| 198 | int_wren_reg <= int_wren_next;
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| 199 | int_chan_reg <= int_chan_next;
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| 200 | int_case_reg <= int_case_next;
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| 201 | int_addr_reg <= int_addr_next;
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| 202 | for(i = 0; i <= 6; i = i + 1)
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| 203 | begin
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| 204 | acc_data_reg[i] <= acc_data_next[i];
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| 205 | end
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| 206 | for(i = 0; i <= 17; i = i + 1)
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| 207 | begin
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| 208 | int_data_reg[i] <= int_data_next[i];
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| 209 | end
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| 210 | end
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| 211 | end
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| 212 |
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| 213 | always @*
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| 214 | begin
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| 215 | int_wren_next = int_wren_reg;
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| 216 | int_chan_next = int_chan_reg;
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| 217 | int_case_next = int_case_reg;
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| 218 | int_addr_next = int_addr_reg;
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| 219 | for(i = 0; i <= 6; i = i + 1)
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| 220 | begin
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| 221 | acc_data_next[i] = acc_data_reg[i];
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| 222 | end
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| 223 | for(i = 0; i <= 17; i = i + 1)
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| 224 | begin
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| 225 | int_data_next[i] = int_data_reg[i];
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| 226 | end
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| 227 |
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| 228 | case (int_case_reg)
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| 229 | 0:
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| 230 | begin
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| 231 | // write zeros
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| 232 | int_wren_next = 1'b1;
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| 233 | int_addr_next = 8'd0;
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| 234 | for(i = 0; i <= 6; i = i + 1)
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| 235 | begin
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| 236 | acc_data_next[i] = {(size*widthr){1'b0}};
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| 237 | end
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| 238 | for(i = 0; i <= 17; i = i + 1)
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| 239 | begin
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| 240 | int_data_next[i] = {(size*widthr){1'b0}};
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| 241 | end
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| 242 | int_case_next = 3'd1;
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| 243 | end
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| 244 | 1:
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| 245 | begin
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| 246 | // write zeros
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| 247 | int_addr_next = int_addr_reg + 8'd1;
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| 248 | if (&int_addr_reg)
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| 249 | begin
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| 250 | int_wren_next = 1'b0;
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| 251 | int_chan_next = 2'd0;
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| 252 | int_case_next = 3'd2;
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| 253 | end
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| 254 | end
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| 255 | 2: // frame
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| 256 | begin
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| 257 | if (frame)
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| 258 | begin
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| 259 | int_wren_next = 1'b1;
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| 260 |
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| 261 | int_addr_next[7:6] = 2'd0;
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| 262 |
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| 263 | // set read addr for 2nd pipeline
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| 264 | int_chan_next = 2'd1;
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| 265 |
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| 266 | // register input data for 2nd and 3rd sums
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| 267 | int_data_next[0] = int_data_wire[1];
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| 268 | int_data_next[1] = int_data_wire[2];
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| 269 |
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| 270 | // prepare registers for 1st sum
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| 271 | acc_data_next[0] = int_data_wire[0];
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| 272 | acc_data_next[1] = int_data_reg[2];
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| 273 | acc_data_next[2] = int_data_reg[3];
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| 274 | acc_data_next[3] = int_data_reg[4];
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| 275 | acc_data_next[4] = int_data_reg[5];
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| 276 | acc_data_next[5] = mul_data_wire[0];
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| 277 | acc_data_next[6] = mul_data_wire[1];
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| 278 |
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| 279 | int_case_next = 3'd3;
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| 280 | end
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| 281 |
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| 282 | end
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| 283 | 3: // 1st sum
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| 284 | begin
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| 285 | int_addr_next[7:6] = 2'd1;
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| 286 |
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| 287 | // set read addr for 3rd pipeline
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| 288 | int_chan_next = 2'd2;
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| 289 |
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| 290 | // prepare registers for 2nd sum
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| 291 | acc_data_next[0] = int_data_reg[0];
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| 292 | acc_data_next[1] = int_data_reg[7];
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| 293 | acc_data_next[2] = int_data_reg[8];
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| 294 | acc_data_next[3] = int_data_reg[9];
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| 295 | acc_data_next[4] = int_data_reg[10];
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| 296 | acc_data_next[5] = mul_data_wire[2];
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| 297 | acc_data_next[6] = mul_data_wire[3];
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| 298 |
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| 299 | // register 1st sum
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| 300 | int_data_next[2] = int_data_wire[4];
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| 301 | int_data_next[3] = int_data_wire[5];
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| 302 | int_data_next[4] = int_data_wire[6];
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| 303 | int_data_next[5] = int_data_wire[7];
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| 304 | int_data_next[6] = int_data_wire[8];
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| 305 |
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| 306 | int_case_next = 3'd4;
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| 307 | end
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| 308 | 4: // 2nd sum
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| 309 | begin
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| 310 | int_addr_next[7:6] = 2'd2;
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| 311 |
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| 312 | // prepare registers for 3rd sum
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| 313 | acc_data_next[0] = int_data_reg[1];
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| 314 | acc_data_next[1] = int_data_reg[12];
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| 315 | acc_data_next[2] = int_data_reg[13];
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| 316 | acc_data_next[3] = int_data_reg[14];
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| 317 | acc_data_next[4] = int_data_reg[15];
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| 318 | acc_data_next[5] = mul_data_wire[4];
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| 319 | acc_data_next[6] = mul_data_wire[5];
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| 320 |
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| 321 | // register 2nd sum
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| 322 | int_data_next[7] = int_data_wire[4];
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| 323 | int_data_next[8] = int_data_wire[5];
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| 324 | int_data_next[9] = int_data_wire[6];
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| 325 | int_data_next[10] = int_data_wire[7];
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| 326 | int_data_next[11] = int_data_wire[8];
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| 327 |
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| 328 | int_case_next = 3'd5;
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| 329 | end
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| 330 | 5: // 3rd sum
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| 331 | begin
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| 332 | int_wren_next = 1'b0;
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| 333 |
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| 334 | // set read addr for 1st pipeline
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| 335 | int_chan_next = 2'd0;
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| 336 |
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| 337 | // register 3rd sum
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| 338 | int_data_next[12] = int_data_wire[4];
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| 339 | int_data_next[13] = int_data_wire[5];
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| 340 | int_data_next[14] = int_data_wire[6];
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| 341 | int_data_next[15] = int_data_wire[7];
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| 342 | int_data_next[16] = int_data_wire[8];
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| 343 |
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| 344 | int_addr_next[5:0] = int_addr_reg[5:0] + 6'd1;
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| 345 |
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| 346 | int_case_next = 3'd2;
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| 347 | end
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| 348 | default:
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| 349 | begin
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| 350 | int_case_next = 3'd0;
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| 351 | end
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| 352 | endcase
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| 353 | end
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| 354 |
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| 355 | assign out_data = {int_data_next[16], int_data_next[11], int_data_next[6]};
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| 356 |
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| 357 | endmodule
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