[146] | 1 |
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| 2 | (* ALTERA_ATTRIBUTE = {"{-to int_data_p} DDIO_INPUT_REGISTER=HIGH; {-to int_data_n} DDIO_INPUT_REGISTER=LOW"} *)
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| 3 |
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[41] | 4 | module adc_lvds
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[63] | 5 | #(
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[140] | 6 | parameter size = 8, // number of channels
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| 7 | parameter width = 24 // channel resolution
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[63] | 8 | )
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[41] | 9 | (
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[107] | 10 | input wire clock,
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| 11 |
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[63] | 12 | input wire lvds_dco,
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| 13 | input wire lvds_fco,
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[72] | 14 | input wire [size-1:0] lvds_d,
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[41] | 15 |
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[107] | 16 | output wire adc_frame,
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[140] | 17 | output wire [size*width-1:0] adc_data
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[107] | 18 |
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[41] | 19 | );
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[140] | 20 |
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[107] | 21 | reg state, int_rdreq, adc_frame_reg;
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| 22 | wire int_wrfull, int_rdempty;
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[41] | 23 |
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[140] | 24 | reg [size-1:0] int_data_p, int_data_n;
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[63] | 25 |
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[147] | 26 | reg [size*width-1:0] int_data_reg;
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| 27 | wire [size*width-1:0] int_data_wire;
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[107] | 28 |
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[140] | 29 | wire [size*width-1:0] int_q_wire;
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| 30 | reg [size*width-1:0] adc_data_reg;
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[107] | 31 |
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| 32 |
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[140] | 33 |
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[63] | 34 | genvar j;
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| 35 |
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[107] | 36 | generate
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[140] | 37 | for (j = 0; j < size; j = j + 1)
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[107] | 38 | begin : INT_DATA
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[140] | 39 | // MSB first
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| 40 | // assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_p[j], int_data_n[j]};
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| 41 | // LSB first
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[147] | 42 | assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]};
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[107] | 43 | end
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| 44 | endgenerate
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| 45 |
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| 46 | dcfifo #(
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[41] | 47 | .intended_device_family("Cyclone III"),
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[107] | 48 | .lpm_numwords(16),
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| 49 | .lpm_showahead("ON"),
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| 50 | .lpm_type("dcfifo"),
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[140] | 51 | .lpm_width(size*width),
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[107] | 52 | .lpm_widthu(4),
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| 53 | .rdsync_delaypipe(4),
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| 54 | .wrsync_delaypipe(4),
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| 55 | .overflow_checking("ON"),
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| 56 | .underflow_checking("ON"),
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| 57 | .use_eab("ON")) fifo_unit (
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[147] | 58 | .data(int_data_wire),
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[107] | 59 | .rdclk(clock),
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| 60 | .rdreq((~int_rdempty) & int_rdreq),
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| 61 | .wrclk(lvds_fco),
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| 62 | .wrreq(~int_wrfull),
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| 63 | .q(int_q_wire),
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| 64 | .rdempty(int_rdempty),
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| 65 | .wrfull(int_wrfull),
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| 66 | .aclr(),
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| 67 | .rdfull(),
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| 68 | .rdusedw(),
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| 69 | .wrempty(),
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| 70 | .wrusedw());
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[41] | 71 |
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[107] | 72 | always @ (posedge clock)
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[41] | 73 | begin
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[107] | 74 | case (state)
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| 75 | 1'b0:
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| 76 | begin
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| 77 | int_rdreq <= 1'b1;
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| 78 | adc_frame_reg <= 1'b0;
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| 79 | state <= 1'b1;
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| 80 | end
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| 81 |
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| 82 | 1'b1:
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| 83 | begin
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| 84 | if (~int_rdempty)
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| 85 | begin
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| 86 | int_rdreq <= 1'b0;
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| 87 | adc_frame_reg <= 1'b1;
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| 88 | adc_data_reg <= int_q_wire;
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| 89 | state <= 1'b0;
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| 90 | end
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| 91 | end
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| 92 | endcase
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[42] | 93 | end
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[107] | 94 |
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| 95 | always @ (negedge lvds_dco)
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[42] | 96 | begin
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[140] | 97 | int_data_n <= lvds_d;
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[41] | 98 | end
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| 99 |
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[107] | 100 | always @ (posedge lvds_dco)
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[42] | 101 | begin
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[140] | 102 | int_data_p <= lvds_d;
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[107] | 103 | int_data_reg <= int_data_wire;
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[147] | 104 |
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[42] | 105 | end
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[41] | 106 |
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[107] | 107 | assign adc_frame = adc_frame_reg;
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| 108 | assign adc_data = adc_data_reg;
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[63] | 109 |
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[58] | 110 | endmodule
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