Timeline



Dec 24, 2009:

7:29 PM Changeset [89] by demin
remove debug output
7:27 PM Changeset [88] by demin
fix memory read timing

Dec 21, 2009:

11:56 PM Changeset [87] by demin
fix writing of the last EPT sample to SRAM
11:55 PM Changeset [86] by demin
replace 3 ADC FIFO with one large FIFO
5:13 PM Changeset [85] by demin
add possibility to record full EPT information
5:09 PM Changeset [84] by demin
improve timings in all components

Nov 30, 2009:

12:51 PM Changeset [83] by demin
first working version
12:36 PM Changeset [82] by demin
several minor fixes
12:34 PM Changeset [81] by demin
activate all 3 ADC channels
12:38 AM Changeset [80] by demin
simplify analyser interface
12:36 AM Changeset [79] by demin
switch from 8 to 4 byte command
12:34 AM Changeset [78] by demin
make configuration frame always visible

Nov 29, 2009:

11:11 PM Changeset [77] by demin
add configuration form and activate all channels

Nov 28, 2009:

2:12 AM Changeset [76] by demin
add counter between peaks

Nov 26, 2009:

12:16 AM Changeset [75] by demin
fix osc_mux and trg_mux
12:15 AM Changeset [74] by demin
fix signal shape display configuration
Note: See TracTimeline for information about the timeline view.