Index: /trunk/MultiChannelUSB/adc_fifo.v
===================================================================
--- /trunk/MultiChannelUSB/adc_fifo.v	(revision 96)
+++ /trunk/MultiChannelUSB/adc_fifo.v	(revision 97)
@@ -4,9 +4,9 @@
 	)
 	(
-		input	wire			adc_clk,
+		input	wire			adc_clock,
 		input	wire	[W-1:0]	adc_data,
 
-		input	wire			sys_clk,
-		output	wire			sys_good,
+		input	wire			sys_clock,
+		output	wire			sys_frame,
 		output	wire	[W-1:0]	sys_data
 	);
@@ -15,5 +15,5 @@
 	reg		[W-1:0]	int_data;
 	
-	reg				state, int_rdreq, int_good;
+	reg				state, int_rdreq, int_frame;
 	wire			int_wrfull, int_rdempty;
 
@@ -33,7 +33,7 @@
 		.aclr(1'b0),
 		.data(adc_data),
-		.rdclk(sys_clk),
+		.rdclk(sys_clock),
 		.rdreq((~int_rdempty) & int_rdreq),
-		.wrclk(adc_clk),
+		.wrclk(adc_clock),
 		.wrreq(~int_wrfull),
 		.q(int_q),
@@ -45,5 +45,5 @@
 		.wrusedw());
 
-	always @(posedge sys_clk)
+	always @(posedge sys_clock)
 	begin
 		case (state)
@@ -51,5 +51,5 @@
 			begin
 				int_rdreq <= 1'b1;
-				int_good <= 1'b0;
+				int_frame <= 1'b0;
 				state <= 1'b1;
 			end
@@ -61,5 +61,5 @@
 					int_data <= int_q;
 					int_rdreq <= 1'b0;
-					int_good <= 1'b1;
+					int_frame <= 1'b1;
 					state <= 1'b0;
 				end
@@ -68,5 +68,5 @@
 	end
 	
-	assign	sys_good = int_good;
+	assign	sys_frame = int_frame;
 	assign	sys_data = int_data;