Index: /trunk/MultiChannelUSB/oscilloscope.v
===================================================================
--- /trunk/MultiChannelUSB/oscilloscope.v	(revision 95)
+++ /trunk/MultiChannelUSB/oscilloscope.v	(revision 96)
@@ -3,5 +3,5 @@
 		input	wire			clock, frame, reset,
 		
-		input	wire	[16:0]  cfg_data,
+		input	wire			cfg_data,
 
 		input	wire			trg_flag,
@@ -32,7 +32,4 @@
 	reg		[19:0]	int_cntr_next [1:0];
 
-	reg		[15:0]	bus_mosi_reg [2:0];
-	reg		[15:0]	bus_mosi_next [2:0];
-
 	reg		[15:0]	bus_miso_reg, bus_miso_next;
 	reg				bus_busy_reg, bus_busy_next;
@@ -41,5 +38,7 @@
 	reg				ram_wren_next [2:0];
 
-	reg		[17:0]	ram_data_reg, ram_data_next;
+	reg		[17:0]	ram_data_reg [2:0];
+	reg		[17:0]	ram_data_next [2:0];
+
 	reg		[19:0]	ram_addr_reg, ram_addr_next;
 
@@ -56,5 +55,5 @@
 		begin : SRAM_WREN
 			assign ram_wren_wire[j] = ram_wren_reg[2];
-			assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[j] : 1'bz;
+			assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[2][j] : 1'bz;
 		end
 	endgenerate
@@ -65,5 +64,4 @@
 		begin
 			osc_data_reg <= 48'd0;
-			ram_data_reg <= 18'd0;
 			ram_addr_reg <= 20'd0;
 			bus_miso_reg <= 16'd0;
@@ -78,5 +76,5 @@
 			begin
 				ram_wren_reg[i] <= 1'b0;
-				bus_mosi_reg[i] <= 16'd0;
+				ram_data_reg[i] <= 16'd0;
 			end
 		end
@@ -84,5 +82,4 @@
 		begin
 			osc_data_reg <= osc_data_next;
-			ram_data_reg <= ram_data_next;
 			ram_addr_reg <= ram_addr_next;
 			bus_miso_reg <= bus_miso_next;
@@ -97,5 +94,5 @@
 			begin
 				ram_wren_reg[i] <= ram_wren_next[i];
-				bus_mosi_reg[i] <= bus_mosi_next[i];
+				ram_data_reg[i] <= ram_data_next[i];
 			end
 		end
@@ -106,5 +103,4 @@
 
 		osc_data_next = osc_data_reg;
-		ram_data_next = ram_data_reg;
 		ram_addr_next = ram_addr_reg;
 		bus_miso_next = bus_miso_reg;
@@ -119,14 +115,12 @@
 		begin
 			ram_wren_next[i+1] = ram_wren_reg[i];
-			bus_mosi_next[i+1] = bus_mosi_reg[i];
+			ram_data_next[i+1] = ram_data_reg[i];
 		end
 		ram_wren_next[0] = 1'b0;
-		bus_mosi_next[0] = 16'd0;
+		ram_data_next[0] = 18'd0;
 
 		case (int_case_reg)
 			0:
 			begin
-				ram_data_next = 18'd0;
-				ram_addr_next = 20'd0;
 				bus_busy_next = 1'b0;
 				int_cntr_next[0] = 20'd0;
@@ -134,6 +128,4 @@
 				int_trig_next = 1'b0;
 
-				ram_data_next = {bus_mosi_reg[1][15:8], 1'b0, bus_mosi_reg[1][7:0], 1'b0};
-
 				if (bus_ssel)
 				begin
@@ -143,78 +135,103 @@
 					begin
 						ram_addr_next = bus_addr;
-						bus_mosi_next[0] = bus_mosi;
+						ram_data_next[0] = {bus_mosi[15:8], 1'b0, bus_mosi[7:0], 1'b0};
 					end
 					else
 					begin
-//						ram_addr_next = int_trig_addr_reg + bus_addr;	
-						ram_addr_next = bus_addr;	
-					end
-				end
-				else if (cfg_data[16])
+						ram_addr_next = int_trig_addr_reg + bus_addr;	
+//						ram_addr_next = bus_addr;	
+					end
+				end
+				else if (cfg_data)
 				begin
 					// start recording
 					ram_wren_next[0] = 1'b1;
+					ram_data_next[0] = 18'd0;
+					ram_addr_next = 20'd0;
 					bus_busy_next = 1'b1;
 					int_case_next = 3'd1;
 					int_trig_addr_next = 20'd0;
-					int_cntr_next[0] = {cfg_data[7:0], 10'd0};
-					int_cntr_next[1] = {cfg_data[15:8], 10'd0};
-				end
-
+//					int_cntr_next[0] = {cfg_data[7:0], 10'd0};
+					int_cntr_next[0] = 20'd262143;
+//					int_cntr_next[1] = {cfg_data[15:8], 10'd0};
+					int_cntr_next[1] = 20'd5000;
+				end
+
+			end
+
+			// write zeros
+			1:
+			begin
+				ram_wren_next[0] = 1'b1;
+				ram_data_next[0] = 18'd2;
+				if(&ram_addr_reg)
+				begin
+					int_case_next = 3'd2;
+				end
+				else
+				begin
+					ram_addr_next = ram_addr_reg + 20'd1;
+				end
 			end
 
 			// sample recording
-			1:
-			begin
-				ram_wren_next[0] = 1'b1;
+			2:
+			begin
 				if (frame)
 				begin
 					osc_data_next = osc_data;
 					ram_addr_next = ram_addr_reg + 20'd1;
+					ram_wren_next[0] = 1'b1;
+					ram_data_next[0] = {osc_data[15:8], 1'b0, osc_data[7:0], 1'b0};
+		
+					int_case_next = 3'd3;
+
+					if (|int_cntr_reg[1])
+					begin
+						int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
+						int_cntr_next[1] = int_cntr_reg[1] - 20'd1;
+					end
+					else if (int_trig_reg)
+					begin
+						if (|int_cntr_reg[0])
+						begin
+							int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
+						end
+					end
+					else if (trg_flag)
+					begin
+						int_trig_next = 1'b1;
+						int_trig_addr_next = ram_addr_reg - 20'd19999;
+					end
+				end
+			end
+
+			3:
+			begin
+				ram_addr_next = ram_addr_reg + 20'd1;
+				ram_wren_next[0] = 1'b1;
+				ram_data_next[0] = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};
+				int_case_next = 3'd4;
+			end
+
+			4:
+			begin
+				ram_addr_next = ram_addr_reg + 20'd1;
+				ram_wren_next[0] = 1'b1;
+				ram_data_next[0] = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
+				int_case_next = 3'd5;
+			end
+
+			5:
+			begin
+				ram_addr_next = ram_addr_reg + 20'd1;
+				ram_wren_next[0] = 1'b1;
+				ram_data_next[0] = 18'd0;
+				if (|int_cntr_reg[0])
+				begin
 					int_case_next = 3'd2;
-
-					if ((~int_trig_reg) & (trg_flag) & (int_cntr_reg[1] == 0))
-					begin
-						int_trig_next = 1'b1;
-						int_trig_addr_next = ram_addr_reg;
-					end
-					
-					if ((int_trig_reg) & (|int_cntr_reg[0]))
-					begin
-						int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
-					end
-
-					if ((|int_cntr_reg[1]))
-					begin
-						int_cntr_next[1] = int_cntr_reg[1] - 20'd1;
-					end
-				end
-			end
-
-			2:
-			begin
-				ram_wren_next[0] = 1'b1;
-				ram_data_next = {osc_data_reg[15:8], 1'b0, osc_data_reg[7:0], 1'b0};
-				ram_addr_next = ram_addr_reg + 20'd1;
-				int_case_next = 3'd3;
-			end
-
-			3:
-			begin
-				ram_wren_next[0] = 1'b1;
-				ram_data_next = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};
-				ram_addr_next = ram_addr_reg + 20'd1;
-				int_case_next = 3'd4;
-			end
-
-			4:
-			begin
-				ram_wren_next[0] = 1'b1;
-				ram_data_next = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
-				int_case_next = 3'd1;
-				if (int_cntr_reg[0] == 0)
-				begin
-					ram_wren_next[0] = 1'b0;
-					ram_addr_next = 20'd0;
+				end
+				else
+				begin
 					int_case_next = 3'd0;
 				end