Index: trunk/MultiChannelUSB/histogram.v
===================================================================
--- trunk/MultiChannelUSB/histogram.v	(revision 88)
+++ trunk/MultiChannelUSB/histogram.v	(revision 90)
@@ -1,20 +1,33 @@
 module histogram
-	#(
-		parameter	W	=	32 // bin resolution
-	)
 	(
-		input	wire			clk, reset,
-		input	wire			data_ready,
-		input	wire	[11:0]  data, address,
-		output	wire	[W-1:0]  q
+		input	wire			clock, frame, reset,
+		
+		input	wire	[40:0]  cfg_data,
+		
+		input	wire			hst_good,
+		input	wire	[11:0]  hst_data,
+
+		input	wire			bus_ssel, bus_wren,
+		input	wire	[12:0]	bus_addr,
+		input	wire	[15:0]	bus_mosi,
+
+		output	wire	[15:0]	bus_miso,
+		output	wire			bus_busy
 	);
 	
 	// signal declaration
-	reg		[3:0]	state_reg, state_next;
-	reg				wren_reg, wren_next;
-	reg		[11:0]	addr_reg, addr_next;
-	reg		[W-1:0]	data_reg, data_next;
-
-	wire	[W-1:0]	q_a_wire, q_b_wire;
+	reg		[3:0]	int_case_reg, int_case_next;
+	reg				int_wren_reg, int_wren_next;
+	reg		[11:0]	int_addr_reg, int_addr_next;
+	reg		[31:0]	int_data_reg, int_data_next;
+
+	reg		[12:0]	bus_addr_reg, bus_addr_next;
+	reg		[15:0]	bus_miso_reg, bus_miso_next;
+
+	reg				bus_wren_reg, bus_wren_next;
+	reg		[15:0]	bus_mosi_reg, bus_mosi_next;
+
+	wire	[31:0]	q_a_wire;
+	wire	[15:0]	q_b_wire;
 
 	altsyncram #(
@@ -28,5 +41,5 @@
 		.lpm_type("altsyncram"),
 		.numwords_a(4096),
-		.numwords_b(4096),
+		.numwords_b(8192),
 		.operation_mode("BIDIR_DUAL_PORT"),
 		.outdata_aclr_a("NONE"),
@@ -36,18 +49,20 @@
 		.power_up_uninitialized("FALSE"),
 		.read_during_write_mode_mixed_ports("OLD_DATA"),
+		.read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
+		.read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
 		.widthad_a(12),
-		.widthad_b(12),
-		.width_a(W),
-		.width_b(W),
+		.widthad_b(13),
+		.width_a(32),
+		.width_b(16),
 		.width_byteena_a(1),
 		.width_byteena_b(1),
 		.wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
-		.wren_a(wren_reg),
-		.clock0(clk),
-		.wren_b(1'b0),
-		.address_a(addr_reg),
-		.address_b(address),
-		.data_a(data_reg),
-		.data_b(),
+		.wren_a(int_wren_reg),
+		.clock0(clock),
+		.wren_b(bus_wren_reg),
+		.address_a(int_addr_reg),
+		.address_b(bus_addr_reg),
+		.data_a(int_data_reg),
+		.data_b(bus_mosi_reg),
 		.q_a(q_a_wire),
 		.q_b(q_b_wire),
@@ -68,19 +83,47 @@
 
 	// body
-	always @(posedge clk)
+	always @(posedge clock)
 	begin
 		if (reset)
         begin
-			wren_reg <= 1'b1;
-			addr_reg <= 12'd0;
-			data_reg <= 32'd0;
-			state_reg <= 4'b1;
+			int_wren_reg <= 1'b1;
+			int_addr_reg <= 12'd0;
+			int_data_reg <= 32'd0;
+			int_case_reg <= 4'b1;
+			bus_addr_reg <= 13'd0;
+			bus_miso_reg <= 16'd0;
+			bus_wren_reg <= 1'b0;
+			bus_mosi_reg <= 16'd0;
 		end
 		else
 		begin
-			wren_reg <= wren_next;
-			addr_reg <= addr_next;
-			data_reg <= data_next;
-			state_reg <= state_next;
+			int_wren_reg <= int_wren_next;
+			int_addr_reg <= int_addr_next;
+			int_data_reg <= int_data_next;
+			int_case_reg <= int_case_next;
+			bus_addr_reg <= bus_addr_next;
+			bus_miso_reg <= bus_miso_next;
+			bus_wren_reg <= bus_wren_next;
+			bus_mosi_reg <= bus_mosi_next;
+		end             
+	end
+
+	always @*
+	begin
+		bus_addr_next = bus_addr_reg;
+		bus_miso_next = bus_miso_reg;
+
+		bus_wren_next = 1'b0;
+		bus_mosi_next = bus_mosi_reg;
+
+		if (bus_ssel)
+		begin
+			bus_miso_next = q_b_wire;	
+			bus_addr_next = bus_addr;
+			bus_wren_next = bus_wren;	
+			if (bus_wren)
+			begin
+				bus_mosi_next = bus_mosi;
+			end
 		end
 	end
@@ -88,16 +131,15 @@
 	always @*
 	begin
-		wren_next = wren_reg;
-		addr_next = addr_reg;
-		data_next = data_reg;
-		state_next = state_reg;
-		case (state_reg)
+		int_wren_next = int_wren_reg;
+		int_addr_next = int_addr_reg;
+		int_data_next = int_data_reg;
+		int_case_next = int_case_reg;
+
+		case (int_case_reg)
 			0:
 			begin
-				// nothing to do
-				wren_next = 1'b0;
-				addr_next = 12'd0;
-				data_next = 32'd0;
-				state_next = 4'd0;
+				int_wren_next = 1'b0;
+				int_addr_next = 12'd0;
+				int_data_next = 32'd0;
 			end
 						
@@ -105,12 +147,12 @@
 			begin
 				// write zeros
-				if (&addr_reg)
-				begin
-					wren_next = 1'b0;
-					state_next = 4'd2;
+				if (&int_addr_reg)
+				begin
+					int_wren_next = 1'b0;
+					int_case_next = 4'd2;
 				end
 				else
 				begin
-					addr_next = addr_reg + 12'd1;
+					int_addr_next = int_addr_reg + 12'd1;
 				end
 			end	
@@ -118,9 +160,13 @@
 			2:
 			begin
-				wren_next = 1'b0;
-				if (data_ready)
-				begin
-					addr_next = data;
-					state_next = 4'd3;
+				int_wren_next = 1'b0;
+				if (&int_data_reg)
+				begin
+					int_case_next = 4'd0;
+				end
+				else if (frame & hst_good)
+				begin
+					int_addr_next = hst_data;
+					int_case_next = 4'd3;
 				end
 			end
@@ -128,32 +174,25 @@
 			3:
 			begin
-				state_next = 4'd4;
+				int_case_next = 4'd4;
 			end
 
 			4:
 			begin
-				state_next = 5'd4;
+				int_case_next = 4'd5;
 			end
 
 			5:
 			begin
-				if (&q_a_wire)
-				begin
-					state_next = 4'd0;
-				end
-				else
-				begin
-					wren_next = 1'b1;
-					data_next = q_a_wire + 32'd1;
-					state_next = 4'd2;
-				end
+				int_wren_next = 1'b1;
+				int_data_next = q_a_wire + 32'd1;
+				int_case_next = 4'd2;
 			end
 
 			default:
 			begin
-				wren_next = 1'b0;
-				addr_next = 12'd0;
-				data_next = 32'd0;
-				state_next = 4'd0;
+				int_wren_next = 1'b0;
+				int_addr_next = 12'd0;
+				int_data_next = 32'd0;
+				int_case_next = 4'd0;
 			end
 		endcase
@@ -161,4 +200,5 @@
 
 	// output logic
-	assign	q = q_b_wire;
+	assign	bus_miso = bus_miso_reg;
+	assign	bus_busy = 1'b0;
 endmodule
