Index: trunk/MultiChannelUSB/Paella.v
===================================================================
--- trunk/MultiChannelUSB/Paella.v	(revision 86)
+++ trunk/MultiChannelUSB/Paella.v	(revision 90)
@@ -52,5 +52,5 @@
 	assign	RAM_ADDR	=	20'h00000;
 */
-	assign	RAM_CLK = sys_clk;
+	assign	RAM_CLK = sys_clock;
 	assign	RAM_CE1 = 1'b0;
 
@@ -73,5 +73,4 @@
 
 	wire			usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
-	wire			usb_aclr;
 	wire			usb_tx_wrreq, usb_rx_rdreq;
 	wire			usb_tx_full, usb_rx_empty;
@@ -94,6 +93,5 @@
 		.usb_addr(usb_addr),
 
-		.clk(sys_clk),
-		.aclr(usb_aclr),
+		.clk(sys_clock),
 
 		.tx_full(usb_tx_full),
@@ -106,58 +104,21 @@
 	);
 		
-	reg 			bln_reset [N-1:0];
-	wire	[11:0]	baseline [N-1:0];
-	wire	[11:0]	bln_baseline [N-1:0];
-
-	reg 			ana_reset [N-1:0];
-	wire			ana_peak_ready [N-1:0];
-	wire			ana_peak_debug [N-1:0];
-
-	reg				osc_reset [N-1:0];
-	reg 	[9:0]	osc_addr [N-1:0];
-	wire	[9:0]	osc_start_addr [N-1:0];
-	wire	[15:0]	osc_q [N-1:0];
-	wire			osc_trig [N-1:0];
-
-	wire	[3:0]	osc_mux_sel [N-1:0];
+	wire			ana_good [N-1:0];
+	wire	[11:0]	ana_data [N-1:0];
+	wire	[11:0]	ana_base [N-1:0];
+
 	wire	[11:0]	osc_mux_data [N-1:0];
 
-	wire 			trg_reset [N-1:0];
-	wire	[3:0]	trg_mux_sel [N-1:0];
-	wire	[11:0]	trg_mux_data [N-1:0];
-	wire	[11:0]	trg_thrs [N-1:0];
-
-	reg 			hst_reset [N-1:0];
-	reg 	[11:0]	hst_addr [N-1:0];
-	wire			hst_data_ready [N-1:0];
-	wire	[11:0]	hst_data [N-1:0];
-	wire	[31:0]	hst_q [N-1:0];
-
-
-	wire	[3:0]	hst_mux_sel [N-1:0];
-	wire	[12:0]	hst_mux_data [N-1:0];
-
-	wire	[3:0]	bln_mux_sel [N-1:0];
-	wire	[11:0]	bln_mux_data [N-1:0];
-
-	wire 			mux_reset, mux_type;
-	wire 	[1:0]	mux_chan, mux_byte;
-	wire 	[15:0]	mux_addr;
-	
-	reg		[7:0]	mux_q;
-	reg 	[1:0]	mux_max_byte;
-	reg 	[15:0]	mux_min_addr, mux_max_addr;
+	wire	[11:0]	trg_mux_data;
+	wire			trg_flag;
+
+	wire	[83:0]	int_mux_data [N-1:0];
+
+	wire			sys_clock, sys_frame;
 
 	wire 	[11:0]	adc_data [N-1:0];
-
-	wire			data_ready;
-    wire	[11:0]	data [N-1:0];
     wire	[11:0]	int_data [N-1:0];
-
     wire	[11:0]	cmp_data;
-    
 	wire	[11:0]	nowhere;
-
-	wire			sys_clk;
 
 	wire 	[31:0]	uwt_d1 [N-1:0];
@@ -174,4 +135,6 @@
 	wire 	[1:0]	uwt_flag2 [N-1:0];
 	wire 	[1:0]	uwt_flag3 [N-1:0];
+	
+	wire			i2c_reset;
 
 /*
@@ -179,5 +142,5 @@
 		.lvds_dco(ADC_DCO),
 		.lvds_fco(ADC_FCO),
-		.para_data_ready(CON_CCLK[0]),
+		.para_good(CON_CCLK[0]),
  		.para_data(CON_C[11:0]),
 		.adc_data(adc_data[2]));
@@ -191,12 +154,8 @@
 */
 
-	sys_pll sys_pll_unit(
-		.inclk0(CLK_50MHz),
-		.c0(sys_clk));
-
 	test test_unit(
 		.clk(ADC_FCO),
-		.data(adc_data[2]));
-//		.data(nowhere);
+//		.data(adc_data[2]));
+		.data(nowhere));
 
 	adc_lvds #(
@@ -207,251 +166,185 @@
 		.lvds_fco(ADC_FCO),
 		.lvds_d(ADC_D[2:0]),
-//		.adc_data({	adc_data[2],
-		.adc_data({	nowhere,
+		.adc_data({	adc_data[2],
+//		.adc_data({	nowhere,
 					adc_data[1],
 					adc_data[0] }));
-
-	reg		[15:0]	cfg_memory [31:0];
-	wire	[15:0]	cfg_src_data;
-	wire	[15:0]	cfg_src_addr, cfg_dst_data, cfg_dst_addr;
-
-	wire			cfg_polarity [N-1:0];
-	wire	[11:0]	cfg_baseline [N-1:0];
-	wire	[11:0]	cfg_hst_threshold [N-1:0];
-	wire	[11:0]	cfg_trg_threshold [N-1:0];
+					
+	assign			cmp_data = CON_B[11:0];
+	assign			sys_clock = ADC_DCO;
+	assign			sys_frame = ADC_FCO;
+
+	wire	[15:0]	cfg_bits [15:0];
+	wire	[255:0]	int_cfg_bits;
+
+	wire	[31:0]	cfg_mux_selector;
 
 	wire 			cfg_reset;
 
-	integer j;
-
-	always @(posedge sys_clk)
-	begin
-		if (cfg_reset)
-		begin
-			for(j = 0; j <= 31; j = j + 1)
-			begin
-				cfg_memory[j] <= 16'd0;
-			end
+	wire 	[7:0]	bus_ssel;
+	wire			bus_wren;
+	wire	[31:0]	bus_addr;
+	wire	[15:0]	bus_mosi;
+	wire 	[15:0]	bus_miso [5:0];
+	wire 	[5:0]	bus_busy;
+
+	wire 	[15:0]	mrg_bus_miso;
+	wire 			mrg_bus_busy;
+
+	wire 	[79:0]	int_bus_miso;
+
+	genvar j;
+
+	generate
+		for (j = 0; j < 16; j = j + 1)
+		begin : CONFIGURATION_OUTPUT
+			assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
 		end
-		else
-		begin
-			cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
+	endgenerate
+
+	configuration configuration_unit (
+		.clock(sys_clock),
+		.reset(cfg_reset),
+		.bus_ssel(bus_ssel[0]),
+		.bus_wren(bus_wren),
+		.bus_addr(bus_addr[3:0]),
+		.bus_mosi(bus_mosi),
+		.bus_miso(bus_miso[0]),
+		.bus_busy(bus_busy[0]),
+		.cfg_bits(int_cfg_bits));
+
+	generate
+		for (j = 0; j < 3; j = j + 1)
+		begin : MUX_DATA
+			assign int_mux_data[j] = {
+				{ana_good[j], 11'd0},
+				ana_data[j],
+				ana_base[j],
+				uwt_a3[j][20:9],
+				uwt_a2[j][17:6],
+				uwt_a1[j][14:3],
+				adc_data[j]};
 		end
-	end
-
-	adc_fifo #(.W(48)) adc_fifo_unit (
-		.adc_clk(ADC_FCO),
-		.adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),
-		.clk(sys_clk),
-		.data_ready(data_ready),
-		.data({cmp_data, int_data[2], int_data[1], int_data[0]}));
-
-	genvar i;
+	endgenerate
+
+	assign cfg_mux_selector = {cfg_bits[11], cfg_bits[10]};
+
+	lpm_mux #(
+		.lpm_size(21),
+		.lpm_type("LPM_MUX"),
+		.lpm_width(12),
+		.lpm_widths(5)) trg_mux_unit (
+		.sel(cfg_mux_selector[28:24]),
+		.data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+		.result(trg_mux_data));
 
 	generate
-		for (i = 0; i < N; i = i + 1)
-		begin : MCA_CHAIN
-
-			assign cfg_polarity[i] = cfg_memory[10][4*i];
-			assign cfg_baseline[i] = cfg_memory[11+i][11:0];
-			assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
-			assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
-
-			assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
-			assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
-
-			assign hst_mux_sel[i] = cfg_memory[23+i][3:0];
-			assign bln_mux_sel[i] = cfg_memory[23+i][7:4];
-
-			assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
-
-			uwt_bior31 #(.L(1)) uwt_1_unit (
-				.clk(sys_clk),
-				.data_ready(data_ready),
-				.x({20'h00000, data[i]}),
-				.d(uwt_d1[i]),
-				.a(uwt_a1[i]),
-				.peak(uwt_peak1[i]),
-				.flag(uwt_flag1[i]));
-		
-			uwt_bior31 #(.L(2)) uwt_2_unit (
-				.clk(sys_clk),
-				.data_ready(data_ready),
-				.x(uwt_a1[i]),
-				.d(uwt_d2[i]),
-				.a(uwt_a2[i]),
-				.peak(uwt_peak2[i]),
-				.flag(uwt_flag2[i]));
-		
-			uwt_bior31 #(.L(3)) uwt_3_unit (
-				.clk(sys_clk),
-				.data_ready(data_ready),
-				.x(uwt_a2[i]),
-				.d(uwt_d3[i]),
-				.a(uwt_a3[i]),
-				.peak(uwt_peak3[i]),
-				.flag(uwt_flag3[i]));
-
+		for (j = 0; j < 3; j = j + 1)
+		begin : OSC_CHAIN
+		
 			lpm_mux #(
-				.lpm_size(7),
+				.lpm_size(21),
 				.lpm_type("LPM_MUX"),
 				.lpm_width(12),
-				.lpm_widths(3)) osc_mux_unit (
-				.sel(osc_mux_sel[i][2:0]),
-				.data({	{ana_peak_debug[i], 11'd0},
-						hst_data[i],
-//						uwt_d3[i][11:0],
-						bln_baseline[i],
-						uwt_a3[i][20:9],
-						uwt_a2[i][17:6],
-						uwt_a1[i][14:3],
-						data[i] }),
-				.result(osc_mux_data[i]));
-
-			lpm_mux #(
-				.lpm_size(7),
-				.lpm_type("LPM_MUX"),
-				.lpm_width(12),
-				.lpm_widths(3)) trg_mux_unit (
-				.sel(trg_mux_sel[i][2:0]),
-				.data({	{ana_peak_ready[i], 11'd0},
-						hst_data[i],
-//						uwt_d3[i][11:0],
-						bln_baseline[i],
-						uwt_a3[i][20:9],
-						uwt_a2[i][17:6],
-						uwt_a1[i][14:3],
-						data[i] }),
-				.result(trg_mux_data[i]));
-
-			lpm_mux #(
-				.lpm_size(2),
-				.lpm_type("LPM_MUX"),
-				.lpm_width(13),
-				.lpm_widths(1)) hst_mux_unit (
-				.sel(hst_mux_sel[i][0]),
-				.data({	{uwt_peak3[i][11:0], ana_peak_ready[i]},
-						{data[i], data_ready} }),
-				.result(hst_mux_data[i]));
-	
-			lpm_mux #(
-				.lpm_size(2),
-				.lpm_type("LPM_MUX"),
-				.lpm_width(12),
-				.lpm_widths(1)) bln_mux_unit (
-				.sel(bln_mux_sel[i][0]),
-				.data({bln_baseline[i], cfg_baseline[i]}),
-				.result(bln_mux_data[i]));
-
-			baseline baseline_unit (
-				.clk(sys_clk),
-				.reset(bln_reset[i]),
-				.data_ready(data_ready),
-				.uwt_flag(uwt_flag3[i]),
-				.uwt_data(uwt_peak3[i]),
-				.baseline(bln_baseline[i]));
-
-			analyser analyser_unit (
-				.clk(sys_clk),
-				.reset(ana_reset[i]),
-				.data_ready(data_ready),
-				.uwt_flag(uwt_flag3[i]),
-				.peak_ready(ana_peak_ready[i]),
-				.peak_debug(ana_peak_debug[i]));
-
-			suppression suppression_unit (
-				.clk(sys_clk),
-				.data(hst_mux_data[i][12:1]),
-				.baseline(bln_mux_data[i]),
-				.result(hst_data[i]));
-
-			assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
-
-			histogram #(.W(32)) histogram_unit (
-				.clk(sys_clk),
-				.reset(hst_reset[i]),
-				.data_ready(hst_data_ready[i]),
-				.data(hst_data[i]),
-				.address(hst_addr[i]),
-				.q(hst_q[i]));
-
-			trigger trigger_unit (
-				.clk(sys_clk),
-				.reset(trg_reset[i]),
-				.data_ready(data_ready),
-				.data(trg_mux_data[i]),
-				.threshold(cfg_trg_threshold[i]),
-				.trigger(osc_trig[i]));
-
-			
-			oscilloscope oscilloscope_unit (
-				.clk(sys_clk),
-				.reset(osc_reset[i]),
-				.data_ready(data_ready),
-				.data(osc_mux_data[i]),
-				.trigger(osc_trig[i]),
-				.address(osc_addr[i]),
-				.start_address(osc_start_addr[i]),
-				.q(osc_q[i]));
+				.lpm_widths(5)) osc_mux_unit (
+				.sel(cfg_mux_selector[j*8+4:j*8]),
+				.data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+				.result(osc_mux_data[j]));
+		
 		end
 	endgenerate
 
-	always @*
-	begin
-		for (j = 0; j < N; j = j + 1)
-		begin
-			osc_reset[j] = 1'b0;
-			osc_addr[j] = 10'b0;
-			hst_reset[j] = 1'b0;
-			hst_addr[j] = 12'b0;
+	trigger trigger_unit (
+		.clock(sys_clock),
+		.frame(sys_frame),
+		.reset(cfg_bits[12][14]),
+		.cfg_data(cfg_bits[12][11:0]),
+		.trg_data(trg_mux_data),
+		.trg_flag(trg_flag));
+	
+	oscilloscope oscilloscope_unit (
+		.clock(sys_clock),
+		.frame(sys_frame),
+		.reset(cfg_bits[12][13]),
+		.cfg_data({cfg_bits[12][12], cfg_bits[13]}),
+		.trg_flag(trg_flag),
+		.osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
+		.ram_wren(RAM_WE),
+		.ram_addr(RAM_ADDR),
+		.ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
+		.bus_ssel(bus_ssel[1]),
+		.bus_wren(bus_wren),
+		.bus_addr(bus_addr[19:0]),
+		.bus_mosi(bus_mosi),
+		.bus_miso(bus_miso[1]),
+		.bus_busy(bus_busy[1]));
+
+	generate
+		for (j = 0; j < 3; j = j + 1)
+		begin : MCA_CHAIN
+
+			assign int_data[j] = (cfg_bits[0][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
+
+			uwt_bior31 #(.L(1)) uwt_1_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+				.x({20'h00000, int_data[j]}),
+				.d(uwt_d1[j]),
+				.a(uwt_a1[j]),
+				.peak(uwt_peak1[j]),
+				.flag(uwt_flag1[j]));
+		
+			uwt_bior31 #(.L(2)) uwt_2_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+				.x(uwt_a1[j]),
+				.d(uwt_d2[j]),
+				.a(uwt_a2[j]),
+				.peak(uwt_peak2[j]),
+				.flag(uwt_flag2[j]));
+		
+			uwt_bior31 #(.L(3)) uwt_3_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+				.x(uwt_a2[j]),
+				.d(uwt_d3[j]),
+				.a(uwt_a3[j]),
+				.peak(uwt_peak3[j]),
+				.flag(uwt_flag3[j]));
+	
+			analyser analyser_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(cfg_bits[2+2*j][12]),
+				.cfg_data({cfg_bits[2+2*j][11:0], cfg_bits[1+2*j][12:0]}),
+				.uwt_flag(uwt_flag3[j]),
+				.uwt_data(uwt_peak3[j]),
+				.ana_good(ana_good[j]),
+				.ana_data(ana_data[j]),
+				.ana_base(ana_base[j]));
+
+			histogram histogram_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(cfg_bits[7+j][13]),
+				.cfg_data(cfg_bits[7+j][12:0]),
+				.hst_good(ana_good[j]),
+				.hst_data(ana_data[j]),
+				.bus_ssel(bus_ssel[2+j]),
+				.bus_wren(bus_wren),
+				.bus_addr(bus_addr[12:0]),
+				.bus_mosi(bus_mosi),
+				.bus_miso(bus_miso[2+j]),
+				.bus_busy(bus_busy[2+j]));
+
 		end
-
-		case(mux_type)
-			1'b0:
-			begin
-				osc_reset[mux_chan] = mux_reset;
-				osc_addr[mux_chan] = mux_addr[9:0];
-				mux_max_byte = 2'd1;	
-				mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
-				mux_max_addr = 16'd1023;
-			end
-
-			1'b1:
-			begin
-				hst_reset[mux_chan] = mux_reset;
-				hst_addr[mux_chan] = mux_addr[11:0];
-				mux_max_byte = 2'd3;	
-				mux_min_addr = 16'd0;
-				mux_max_addr = 16'd4095;
-			end
-		endcase
-	end
-	
-	always @*
-	begin
-		case ({mux_type, mux_byte})
-			3'b000: mux_q = osc_q[mux_chan][7:0];
-			3'b001: mux_q = osc_q[mux_chan][15:8];
-
-			3'b100: mux_q = hst_q[mux_chan][7:0];
-			3'b101: mux_q = hst_q[mux_chan][15:8];
-			3'b110: mux_q = hst_q[mux_chan][23:16];
-			3'b111: mux_q = hst_q[mux_chan][31:24];
-
-			default: mux_q = 8'd0;
-		endcase     
-	end
-
-	wire			i2c_aclr;
-	wire			i2c_wrreq;
-	wire			i2c_full;
-	wire 	[15:0]	i2c_data;
+	endgenerate
 
 	i2c_fifo i2c_unit(
-		.clk(sys_clk),
-		.aclr(i2c_aclr),
-		.wrreq(i2c_wrreq),
-		.data(i2c_data),
-		.full(i2c_full),
+		.clock(sys_clock),
+		.reset(i2c_reset),
 /*
 		normal connection
@@ -462,36 +355,69 @@
 */
 		.i2c_sda(I2C_SCL),
-		.i2c_scl(I2C_SDA));
+		.i2c_scl(I2C_SDA),
+		
+		.bus_ssel(bus_ssel[5]),
+		.bus_wren(bus_wren),
+		.bus_mosi(bus_mosi),
+		.bus_busy(bus_busy[5]));
+
+	generate
+		for (j = 0; j < 5; j = j + 1)
+		begin : BUS_OUTPUT
+			assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
+		end
+	endgenerate
+
+	lpm_mux #(
+		.lpm_size(5),
+		.lpm_type("LPM_MUX"),
+		.lpm_width(16),
+		.lpm_widths(3)) bus_miso_mux_unit (
+		.sel(bus_addr[30:28]),
+		.data(int_bus_miso),
+		.result(mrg_bus_miso));
+
+	lpm_mux #(
+		.lpm_size(6),
+		.lpm_type("LPM_MUX"),
+		.lpm_width(1),
+		.lpm_widths(3)) bus_busy_mux_unit (
+		.sel(bus_addr[30:28]),
+		.data(bus_busy),
+		.result(mrg_bus_busy));
+
+/*
+	lpm_or #(
+		.lpm_size(6),
+		.lpm_type("LPM_OR"),
+		.lpm_width(16)) bus_miso_or_unit (
+		.data(int_bus_miso),
+		.result(mrg_bus_miso));
+*/
+
+	lpm_decode #(
+		.lpm_decodes(8),
+		.lpm_type("LPM_DECODE"),
+		.lpm_width(3)) lpm_decode_unit (
+		.data(bus_addr[30:28]),
+		.eq(bus_ssel),
+		.aclr(),
+		.clken(),
+		.clock(),
+		.enable());
 
 	control control_unit (
-		.clk(sys_clk),
-		.cfg_reset(cfg_reset),
-		.cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
-		.cfg_src_addr(cfg_src_addr),
-		.cfg_dst_data(cfg_dst_data),
-		.cfg_dst_addr(cfg_dst_addr),
+		.clock(sys_clock),
 		.rx_empty(usb_rx_empty),
 		.tx_full(usb_tx_full),
 		.rx_data(usb_rx_data),
-		.mux_max_byte(mux_max_byte),
-		.mux_min_addr(mux_min_addr),
-		.mux_max_addr(mux_max_addr),
-		.mux_q(mux_q),
-		.mux_reset(mux_reset),
-		.mux_type(mux_type),
-		.mux_chan(mux_chan),
-		.mux_byte(mux_byte),
-		.mux_addr(mux_addr),
 		.rx_rdreq(usb_rx_rdreq),
 		.tx_wrreq(usb_tx_wrreq),
 		.tx_data(usb_tx_data),
-		.ram_we(RAM_WE),
-		.ram_addr(RAM_ADDR),
-		.ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
-		.ept_data_ready(data_ready),
-		.ept_data({cmp_data, data[2], data[1], data[0]}),
-		.i2c_wrreq(i2c_wrreq),
-		.i2c_data(i2c_data),
-		.i2c_full(i2c_full),
+		.bus_wren(bus_wren),
+		.bus_addr(bus_addr),
+		.bus_mosi(bus_mosi),
+		.bus_miso(mrg_bus_miso),
+		.bus_busy(mrg_bus_busy),
 		.led(LED));
 
