Index: /trunk/MultiChannelUSB/Paella.qsf
===================================================================
--- /trunk/MultiChannelUSB/Paella.qsf	(revision 89)
+++ /trunk/MultiChannelUSB/Paella.qsf	(revision 90)
@@ -56,9 +56,8 @@
 set_global_assignment -name VERILOG_FILE control.v
 set_global_assignment -name VERILOG_FILE analyser.v
-set_global_assignment -name VERILOG_FILE baseline.v
 set_global_assignment -name VERILOG_FILE histogram.v
 set_global_assignment -name VERILOG_FILE trigger.v
-set_global_assignment -name VERILOG_FILE suppression.v
 set_global_assignment -name VERILOG_FILE oscilloscope.v
+set_global_assignment -name VERILOG_FILE configuration.v
 set_global_assignment -name VERILOG_FILE usb_fifo.v
 set_global_assignment -name VERILOG_FILE i2c_fifo.v
Index: /trunk/MultiChannelUSB/Paella.v
===================================================================
--- /trunk/MultiChannelUSB/Paella.v	(revision 89)
+++ /trunk/MultiChannelUSB/Paella.v	(revision 90)
@@ -52,5 +52,5 @@
 	assign	RAM_ADDR	=	20'h00000;
 */
-	assign	RAM_CLK = sys_clk;
+	assign	RAM_CLK = sys_clock;
 	assign	RAM_CE1 = 1'b0;
 
@@ -73,5 +73,4 @@
 
 	wire			usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
-	wire			usb_aclr;
 	wire			usb_tx_wrreq, usb_rx_rdreq;
 	wire			usb_tx_full, usb_rx_empty;
@@ -94,6 +93,5 @@
 		.usb_addr(usb_addr),
 
-		.clk(sys_clk),
-		.aclr(usb_aclr),
+		.clk(sys_clock),
 
 		.tx_full(usb_tx_full),
@@ -106,58 +104,21 @@
 	);
 		
-	reg 			bln_reset [N-1:0];
-	wire	[11:0]	baseline [N-1:0];
-	wire	[11:0]	bln_baseline [N-1:0];
-
-	reg 			ana_reset [N-1:0];
-	wire			ana_peak_ready [N-1:0];
-	wire			ana_peak_debug [N-1:0];
-
-	reg				osc_reset [N-1:0];
-	reg 	[9:0]	osc_addr [N-1:0];
-	wire	[9:0]	osc_start_addr [N-1:0];
-	wire	[15:0]	osc_q [N-1:0];
-	wire			osc_trig [N-1:0];
-
-	wire	[3:0]	osc_mux_sel [N-1:0];
+	wire			ana_good [N-1:0];
+	wire	[11:0]	ana_data [N-1:0];
+	wire	[11:0]	ana_base [N-1:0];
+
 	wire	[11:0]	osc_mux_data [N-1:0];
 
-	wire 			trg_reset [N-1:0];
-	wire	[3:0]	trg_mux_sel [N-1:0];
-	wire	[11:0]	trg_mux_data [N-1:0];
-	wire	[11:0]	trg_thrs [N-1:0];
-
-	reg 			hst_reset [N-1:0];
-	reg 	[11:0]	hst_addr [N-1:0];
-	wire			hst_data_ready [N-1:0];
-	wire	[11:0]	hst_data [N-1:0];
-	wire	[31:0]	hst_q [N-1:0];
-
-
-	wire	[3:0]	hst_mux_sel [N-1:0];
-	wire	[12:0]	hst_mux_data [N-1:0];
-
-	wire	[3:0]	bln_mux_sel [N-1:0];
-	wire	[11:0]	bln_mux_data [N-1:0];
-
-	wire 			mux_reset, mux_type;
-	wire 	[1:0]	mux_chan, mux_byte;
-	wire 	[15:0]	mux_addr;
-	
-	reg		[7:0]	mux_q;
-	reg 	[1:0]	mux_max_byte;
-	reg 	[15:0]	mux_min_addr, mux_max_addr;
+	wire	[11:0]	trg_mux_data;
+	wire			trg_flag;
+
+	wire	[83:0]	int_mux_data [N-1:0];
+
+	wire			sys_clock, sys_frame;
 
 	wire 	[11:0]	adc_data [N-1:0];
-
-	wire			data_ready;
-    wire	[11:0]	data [N-1:0];
     wire	[11:0]	int_data [N-1:0];
-
     wire	[11:0]	cmp_data;
-    
 	wire	[11:0]	nowhere;
-
-	wire			sys_clk;
 
 	wire 	[31:0]	uwt_d1 [N-1:0];
@@ -174,4 +135,6 @@
 	wire 	[1:0]	uwt_flag2 [N-1:0];
 	wire 	[1:0]	uwt_flag3 [N-1:0];
+	
+	wire			i2c_reset;
 
 /*
@@ -179,5 +142,5 @@
 		.lvds_dco(ADC_DCO),
 		.lvds_fco(ADC_FCO),
-		.para_data_ready(CON_CCLK[0]),
+		.para_good(CON_CCLK[0]),
  		.para_data(CON_C[11:0]),
 		.adc_data(adc_data[2]));
@@ -191,12 +154,8 @@
 */
 
-	sys_pll sys_pll_unit(
-		.inclk0(CLK_50MHz),
-		.c0(sys_clk));
-
 	test test_unit(
 		.clk(ADC_FCO),
-		.data(adc_data[2]));
-//		.data(nowhere);
+//		.data(adc_data[2]));
+		.data(nowhere));
 
 	adc_lvds #(
@@ -207,251 +166,185 @@
 		.lvds_fco(ADC_FCO),
 		.lvds_d(ADC_D[2:0]),
-//		.adc_data({	adc_data[2],
-		.adc_data({	nowhere,
+		.adc_data({	adc_data[2],
+//		.adc_data({	nowhere,
 					adc_data[1],
 					adc_data[0] }));
-
-	reg		[15:0]	cfg_memory [31:0];
-	wire	[15:0]	cfg_src_data;
-	wire	[15:0]	cfg_src_addr, cfg_dst_data, cfg_dst_addr;
-
-	wire			cfg_polarity [N-1:0];
-	wire	[11:0]	cfg_baseline [N-1:0];
-	wire	[11:0]	cfg_hst_threshold [N-1:0];
-	wire	[11:0]	cfg_trg_threshold [N-1:0];
+					
+	assign			cmp_data = CON_B[11:0];
+	assign			sys_clock = ADC_DCO;
+	assign			sys_frame = ADC_FCO;
+
+	wire	[15:0]	cfg_bits [15:0];
+	wire	[255:0]	int_cfg_bits;
+
+	wire	[31:0]	cfg_mux_selector;
 
 	wire 			cfg_reset;
 
-	integer j;
-
-	always @(posedge sys_clk)
-	begin
-		if (cfg_reset)
-		begin
-			for(j = 0; j <= 31; j = j + 1)
-			begin
-				cfg_memory[j] <= 16'd0;
-			end
+	wire 	[7:0]	bus_ssel;
+	wire			bus_wren;
+	wire	[31:0]	bus_addr;
+	wire	[15:0]	bus_mosi;
+	wire 	[15:0]	bus_miso [5:0];
+	wire 	[5:0]	bus_busy;
+
+	wire 	[15:0]	mrg_bus_miso;
+	wire 			mrg_bus_busy;
+
+	wire 	[79:0]	int_bus_miso;
+
+	genvar j;
+
+	generate
+		for (j = 0; j < 16; j = j + 1)
+		begin : CONFIGURATION_OUTPUT
+			assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
 		end
-		else
-		begin
-			cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
+	endgenerate
+
+	configuration configuration_unit (
+		.clock(sys_clock),
+		.reset(cfg_reset),
+		.bus_ssel(bus_ssel[0]),
+		.bus_wren(bus_wren),
+		.bus_addr(bus_addr[3:0]),
+		.bus_mosi(bus_mosi),
+		.bus_miso(bus_miso[0]),
+		.bus_busy(bus_busy[0]),
+		.cfg_bits(int_cfg_bits));
+
+	generate
+		for (j = 0; j < 3; j = j + 1)
+		begin : MUX_DATA
+			assign int_mux_data[j] = {
+				{ana_good[j], 11'd0},
+				ana_data[j],
+				ana_base[j],
+				uwt_a3[j][20:9],
+				uwt_a2[j][17:6],
+				uwt_a1[j][14:3],
+				adc_data[j]};
 		end
-	end
-
-	adc_fifo #(.W(48)) adc_fifo_unit (
-		.adc_clk(ADC_FCO),
-		.adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),
-		.clk(sys_clk),
-		.data_ready(data_ready),
-		.data({cmp_data, int_data[2], int_data[1], int_data[0]}));
-
-	genvar i;
+	endgenerate
+
+	assign cfg_mux_selector = {cfg_bits[11], cfg_bits[10]};
+
+	lpm_mux #(
+		.lpm_size(21),
+		.lpm_type("LPM_MUX"),
+		.lpm_width(12),
+		.lpm_widths(5)) trg_mux_unit (
+		.sel(cfg_mux_selector[28:24]),
+		.data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+		.result(trg_mux_data));
 
 	generate
-		for (i = 0; i < N; i = i + 1)
-		begin : MCA_CHAIN
-
-			assign cfg_polarity[i] = cfg_memory[10][4*i];
-			assign cfg_baseline[i] = cfg_memory[11+i][11:0];
-			assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
-			assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
-
-			assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
-			assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
-
-			assign hst_mux_sel[i] = cfg_memory[23+i][3:0];
-			assign bln_mux_sel[i] = cfg_memory[23+i][7:4];
-
-			assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
-
-			uwt_bior31 #(.L(1)) uwt_1_unit (
-				.clk(sys_clk),
-				.data_ready(data_ready),
-				.x({20'h00000, data[i]}),
-				.d(uwt_d1[i]),
-				.a(uwt_a1[i]),
-				.peak(uwt_peak1[i]),
-				.flag(uwt_flag1[i]));
-		
-			uwt_bior31 #(.L(2)) uwt_2_unit (
-				.clk(sys_clk),
-				.data_ready(data_ready),
-				.x(uwt_a1[i]),
-				.d(uwt_d2[i]),
-				.a(uwt_a2[i]),
-				.peak(uwt_peak2[i]),
-				.flag(uwt_flag2[i]));
-		
-			uwt_bior31 #(.L(3)) uwt_3_unit (
-				.clk(sys_clk),
-				.data_ready(data_ready),
-				.x(uwt_a2[i]),
-				.d(uwt_d3[i]),
-				.a(uwt_a3[i]),
-				.peak(uwt_peak3[i]),
-				.flag(uwt_flag3[i]));
-
+		for (j = 0; j < 3; j = j + 1)
+		begin : OSC_CHAIN
+		
 			lpm_mux #(
-				.lpm_size(7),
+				.lpm_size(21),
 				.lpm_type("LPM_MUX"),
 				.lpm_width(12),
-				.lpm_widths(3)) osc_mux_unit (
-				.sel(osc_mux_sel[i][2:0]),
-				.data({	{ana_peak_debug[i], 11'd0},
-						hst_data[i],
-//						uwt_d3[i][11:0],
-						bln_baseline[i],
-						uwt_a3[i][20:9],
-						uwt_a2[i][17:6],
-						uwt_a1[i][14:3],
-						data[i] }),
-				.result(osc_mux_data[i]));
-
-			lpm_mux #(
-				.lpm_size(7),
-				.lpm_type("LPM_MUX"),
-				.lpm_width(12),
-				.lpm_widths(3)) trg_mux_unit (
-				.sel(trg_mux_sel[i][2:0]),
-				.data({	{ana_peak_ready[i], 11'd0},
-						hst_data[i],
-//						uwt_d3[i][11:0],
-						bln_baseline[i],
-						uwt_a3[i][20:9],
-						uwt_a2[i][17:6],
-						uwt_a1[i][14:3],
-						data[i] }),
-				.result(trg_mux_data[i]));
-
-			lpm_mux #(
-				.lpm_size(2),
-				.lpm_type("LPM_MUX"),
-				.lpm_width(13),
-				.lpm_widths(1)) hst_mux_unit (
-				.sel(hst_mux_sel[i][0]),
-				.data({	{uwt_peak3[i][11:0], ana_peak_ready[i]},
-						{data[i], data_ready} }),
-				.result(hst_mux_data[i]));
-	
-			lpm_mux #(
-				.lpm_size(2),
-				.lpm_type("LPM_MUX"),
-				.lpm_width(12),
-				.lpm_widths(1)) bln_mux_unit (
-				.sel(bln_mux_sel[i][0]),
-				.data({bln_baseline[i], cfg_baseline[i]}),
-				.result(bln_mux_data[i]));
-
-			baseline baseline_unit (
-				.clk(sys_clk),
-				.reset(bln_reset[i]),
-				.data_ready(data_ready),
-				.uwt_flag(uwt_flag3[i]),
-				.uwt_data(uwt_peak3[i]),
-				.baseline(bln_baseline[i]));
-
-			analyser analyser_unit (
-				.clk(sys_clk),
-				.reset(ana_reset[i]),
-				.data_ready(data_ready),
-				.uwt_flag(uwt_flag3[i]),
-				.peak_ready(ana_peak_ready[i]),
-				.peak_debug(ana_peak_debug[i]));
-
-			suppression suppression_unit (
-				.clk(sys_clk),
-				.data(hst_mux_data[i][12:1]),
-				.baseline(bln_mux_data[i]),
-				.result(hst_data[i]));
-
-			assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
-
-			histogram #(.W(32)) histogram_unit (
-				.clk(sys_clk),
-				.reset(hst_reset[i]),
-				.data_ready(hst_data_ready[i]),
-				.data(hst_data[i]),
-				.address(hst_addr[i]),
-				.q(hst_q[i]));
-
-			trigger trigger_unit (
-				.clk(sys_clk),
-				.reset(trg_reset[i]),
-				.data_ready(data_ready),
-				.data(trg_mux_data[i]),
-				.threshold(cfg_trg_threshold[i]),
-				.trigger(osc_trig[i]));
-
-			
-			oscilloscope oscilloscope_unit (
-				.clk(sys_clk),
-				.reset(osc_reset[i]),
-				.data_ready(data_ready),
-				.data(osc_mux_data[i]),
-				.trigger(osc_trig[i]),
-				.address(osc_addr[i]),
-				.start_address(osc_start_addr[i]),
-				.q(osc_q[i]));
+				.lpm_widths(5)) osc_mux_unit (
+				.sel(cfg_mux_selector[j*8+4:j*8]),
+				.data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+				.result(osc_mux_data[j]));
+		
 		end
 	endgenerate
 
-	always @*
-	begin
-		for (j = 0; j < N; j = j + 1)
-		begin
-			osc_reset[j] = 1'b0;
-			osc_addr[j] = 10'b0;
-			hst_reset[j] = 1'b0;
-			hst_addr[j] = 12'b0;
+	trigger trigger_unit (
+		.clock(sys_clock),
+		.frame(sys_frame),
+		.reset(cfg_bits[12][14]),
+		.cfg_data(cfg_bits[12][11:0]),
+		.trg_data(trg_mux_data),
+		.trg_flag(trg_flag));
+	
+	oscilloscope oscilloscope_unit (
+		.clock(sys_clock),
+		.frame(sys_frame),
+		.reset(cfg_bits[12][13]),
+		.cfg_data({cfg_bits[12][12], cfg_bits[13]}),
+		.trg_flag(trg_flag),
+		.osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
+		.ram_wren(RAM_WE),
+		.ram_addr(RAM_ADDR),
+		.ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
+		.bus_ssel(bus_ssel[1]),
+		.bus_wren(bus_wren),
+		.bus_addr(bus_addr[19:0]),
+		.bus_mosi(bus_mosi),
+		.bus_miso(bus_miso[1]),
+		.bus_busy(bus_busy[1]));
+
+	generate
+		for (j = 0; j < 3; j = j + 1)
+		begin : MCA_CHAIN
+
+			assign int_data[j] = (cfg_bits[0][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
+
+			uwt_bior31 #(.L(1)) uwt_1_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+				.x({20'h00000, int_data[j]}),
+				.d(uwt_d1[j]),
+				.a(uwt_a1[j]),
+				.peak(uwt_peak1[j]),
+				.flag(uwt_flag1[j]));
+		
+			uwt_bior31 #(.L(2)) uwt_2_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+				.x(uwt_a1[j]),
+				.d(uwt_d2[j]),
+				.a(uwt_a2[j]),
+				.peak(uwt_peak2[j]),
+				.flag(uwt_flag2[j]));
+		
+			uwt_bior31 #(.L(3)) uwt_3_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+				.x(uwt_a2[j]),
+				.d(uwt_d3[j]),
+				.a(uwt_a3[j]),
+				.peak(uwt_peak3[j]),
+				.flag(uwt_flag3[j]));
+	
+			analyser analyser_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(cfg_bits[2+2*j][12]),
+				.cfg_data({cfg_bits[2+2*j][11:0], cfg_bits[1+2*j][12:0]}),
+				.uwt_flag(uwt_flag3[j]),
+				.uwt_data(uwt_peak3[j]),
+				.ana_good(ana_good[j]),
+				.ana_data(ana_data[j]),
+				.ana_base(ana_base[j]));
+
+			histogram histogram_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(cfg_bits[7+j][13]),
+				.cfg_data(cfg_bits[7+j][12:0]),
+				.hst_good(ana_good[j]),
+				.hst_data(ana_data[j]),
+				.bus_ssel(bus_ssel[2+j]),
+				.bus_wren(bus_wren),
+				.bus_addr(bus_addr[12:0]),
+				.bus_mosi(bus_mosi),
+				.bus_miso(bus_miso[2+j]),
+				.bus_busy(bus_busy[2+j]));
+
 		end
-
-		case(mux_type)
-			1'b0:
-			begin
-				osc_reset[mux_chan] = mux_reset;
-				osc_addr[mux_chan] = mux_addr[9:0];
-				mux_max_byte = 2'd1;	
-				mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
-				mux_max_addr = 16'd1023;
-			end
-
-			1'b1:
-			begin
-				hst_reset[mux_chan] = mux_reset;
-				hst_addr[mux_chan] = mux_addr[11:0];
-				mux_max_byte = 2'd3;	
-				mux_min_addr = 16'd0;
-				mux_max_addr = 16'd4095;
-			end
-		endcase
-	end
-	
-	always @*
-	begin
-		case ({mux_type, mux_byte})
-			3'b000: mux_q = osc_q[mux_chan][7:0];
-			3'b001: mux_q = osc_q[mux_chan][15:8];
-
-			3'b100: mux_q = hst_q[mux_chan][7:0];
-			3'b101: mux_q = hst_q[mux_chan][15:8];
-			3'b110: mux_q = hst_q[mux_chan][23:16];
-			3'b111: mux_q = hst_q[mux_chan][31:24];
-
-			default: mux_q = 8'd0;
-		endcase     
-	end
-
-	wire			i2c_aclr;
-	wire			i2c_wrreq;
-	wire			i2c_full;
-	wire 	[15:0]	i2c_data;
+	endgenerate
 
 	i2c_fifo i2c_unit(
-		.clk(sys_clk),
-		.aclr(i2c_aclr),
-		.wrreq(i2c_wrreq),
-		.data(i2c_data),
-		.full(i2c_full),
+		.clock(sys_clock),
+		.reset(i2c_reset),
 /*
 		normal connection
@@ -462,36 +355,69 @@
 */
 		.i2c_sda(I2C_SCL),
-		.i2c_scl(I2C_SDA));
+		.i2c_scl(I2C_SDA),
+		
+		.bus_ssel(bus_ssel[5]),
+		.bus_wren(bus_wren),
+		.bus_mosi(bus_mosi),
+		.bus_busy(bus_busy[5]));
+
+	generate
+		for (j = 0; j < 5; j = j + 1)
+		begin : BUS_OUTPUT
+			assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
+		end
+	endgenerate
+
+	lpm_mux #(
+		.lpm_size(5),
+		.lpm_type("LPM_MUX"),
+		.lpm_width(16),
+		.lpm_widths(3)) bus_miso_mux_unit (
+		.sel(bus_addr[30:28]),
+		.data(int_bus_miso),
+		.result(mrg_bus_miso));
+
+	lpm_mux #(
+		.lpm_size(6),
+		.lpm_type("LPM_MUX"),
+		.lpm_width(1),
+		.lpm_widths(3)) bus_busy_mux_unit (
+		.sel(bus_addr[30:28]),
+		.data(bus_busy),
+		.result(mrg_bus_busy));
+
+/*
+	lpm_or #(
+		.lpm_size(6),
+		.lpm_type("LPM_OR"),
+		.lpm_width(16)) bus_miso_or_unit (
+		.data(int_bus_miso),
+		.result(mrg_bus_miso));
+*/
+
+	lpm_decode #(
+		.lpm_decodes(8),
+		.lpm_type("LPM_DECODE"),
+		.lpm_width(3)) lpm_decode_unit (
+		.data(bus_addr[30:28]),
+		.eq(bus_ssel),
+		.aclr(),
+		.clken(),
+		.clock(),
+		.enable());
 
 	control control_unit (
-		.clk(sys_clk),
-		.cfg_reset(cfg_reset),
-		.cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
-		.cfg_src_addr(cfg_src_addr),
-		.cfg_dst_data(cfg_dst_data),
-		.cfg_dst_addr(cfg_dst_addr),
+		.clock(sys_clock),
 		.rx_empty(usb_rx_empty),
 		.tx_full(usb_tx_full),
 		.rx_data(usb_rx_data),
-		.mux_max_byte(mux_max_byte),
-		.mux_min_addr(mux_min_addr),
-		.mux_max_addr(mux_max_addr),
-		.mux_q(mux_q),
-		.mux_reset(mux_reset),
-		.mux_type(mux_type),
-		.mux_chan(mux_chan),
-		.mux_byte(mux_byte),
-		.mux_addr(mux_addr),
 		.rx_rdreq(usb_rx_rdreq),
 		.tx_wrreq(usb_tx_wrreq),
 		.tx_data(usb_tx_data),
-		.ram_we(RAM_WE),
-		.ram_addr(RAM_ADDR),
-		.ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
-		.ept_data_ready(data_ready),
-		.ept_data({cmp_data, data[2], data[1], data[0]}),
-		.i2c_wrreq(i2c_wrreq),
-		.i2c_data(i2c_data),
-		.i2c_full(i2c_full),
+		.bus_wren(bus_wren),
+		.bus_addr(bus_addr),
+		.bus_mosi(bus_mosi),
+		.bus_miso(mrg_bus_miso),
+		.bus_busy(mrg_bus_busy),
 		.led(LED));
 
Index: /trunk/MultiChannelUSB/adc_fifo.v
===================================================================
--- /trunk/MultiChannelUSB/adc_fifo.v	(revision 89)
+++ /trunk/MultiChannelUSB/adc_fifo.v	(revision 90)
@@ -7,7 +7,7 @@
 		input	wire	[W-1:0]	adc_data,
 
-		input	wire			clk,
-		output	wire			data_ready,
-		output	wire	[W-1:0]	data
+		input	wire			sys_clk,
+		output	wire			sys_good,
+		output	wire	[W-1:0]	sys_data
 	);
 
@@ -15,5 +15,5 @@
 	reg		[W-1:0]	int_data;
 	
-	reg				state, int_rdreq, int_data_ready;
+	reg				state, int_rdreq, int_good;
 	wire			int_wrfull, int_rdempty;
 
@@ -33,5 +33,5 @@
 		.aclr(1'b0),
 		.data(adc_data),
-		.rdclk(clk),
+		.rdclk(sys_clk),
 		.rdreq((~int_rdempty) & int_rdreq),
 		.wrclk(adc_clk),
@@ -45,5 +45,5 @@
 		.wrusedw());
 
-	always @(posedge clk)
+	always @(posedge sys_clk)
 	begin
 		case (state)
@@ -51,5 +51,5 @@
 			begin
 				int_rdreq <= 1'b1;
-				int_data_ready <= 1'b0;
+				int_good <= 1'b0;
 				state <= 1'b1;
 			end
@@ -61,5 +61,5 @@
 					int_data <= int_q;
 					int_rdreq <= 1'b0;
-					int_data_ready <= 1'b1;
+					int_good <= 1'b1;
 					state <= 1'b0;
 				end
@@ -68,6 +68,6 @@
 	end
 	
-	assign	data_ready = int_data_ready;
-	assign	data = int_data;
+	assign	sys_good = int_good;
+	assign	sys_data = int_data;
 
 endmodule
Index: /trunk/MultiChannelUSB/analyser.v
===================================================================
--- /trunk/MultiChannelUSB/analyser.v	(revision 89)
+++ /trunk/MultiChannelUSB/analyser.v	(revision 90)
@@ -1,31 +1,51 @@
 module analyser
 	(
-		input	wire			clk, reset,
-		input	wire			data_ready,
+		input	wire			clock, frame, reset,
+		input	wire	[12:0]	cfg_data,
 		input	wire	[1:0]	uwt_flag,
-		output	wire			peak_ready
+		input	wire	[11:0]	uwt_data,
+		output	wire			ana_good,
+		output	wire	[11:0]	ana_data,
+		output	wire	[11:0]	ana_base
 	);
 
-	reg				flag_reg, flag_next;
-	reg		[1:0]	state_reg, state_next;
+	reg				state_reg, state_next;
 	reg		[4:0]	counter_reg, counter_next;
-	reg				peak_ready_reg;
+	reg				good_reg, good_next;
+	reg		[11:0]	data_reg, data_next;
 
+	reg		[19:0]	buffer_reg [31:0];
+	reg		[19:0]	buffer_next [31:0];
+
+	wire	[19:0]	sample = {8'd0, uwt_data};
+	wire	[11:0]	baseline = buffer_reg[31][16:5];
 	wire			counter_max = (&counter_reg);
-	wire			peak_ready_int = (flag_reg & data_ready & uwt_flag[0] & counter_max);
 
-	always @(posedge clk)
+	integer i;
+
+	always @(posedge clock)
 	begin
 		if (reset)
 		begin
-			flag_reg <= 1'b0;
-			state_reg <= 2'd0;
+			state_reg <= 1'b0;
 			counter_reg <= 5'd0;
+			good_reg <= 1'b0;
+			data_reg <= 12'd0;
+			for(i = 0; i <= 31; i = i + 1)
+			begin
+				buffer_reg[i] <= 20'hfffff;
+			end
 		end
 		else
 		begin
-			flag_reg <= flag_next;
 			state_reg <= state_next;
 			counter_reg <= counter_next;
+			good_reg <= good_next;
+			data_reg <= data_next;
+
+			for(i = 0; i <= 31; i = i + 1)
+			begin
+				buffer_reg[i] <= buffer_next[i];
+			end
 		end
 	end
@@ -33,60 +53,85 @@
 	always @*
 	begin
-		flag_next = flag_reg;
 		state_next = state_reg;
 		counter_next = counter_reg;
+		good_next = good_reg;
+		data_next = data_reg;
+		
+		for(i = 0; i <= 31; i = i + 1)
+		begin
+			buffer_next[i] = buffer_reg[i];
+		end
+
 		case (state_reg)
-			0: // skip first 16 samples
+			0: // skip first 32 samples
 			begin
-				flag_next = 1'b0;
-				if (data_ready)
+				if (frame)
 				begin
 					counter_next = counter_reg + 5'd1;
 					if (counter_max)
 					begin
-						state_next = 2'd1;
+						state_next = 1'b1;
 					end
                 end
  			end
 
-			1: // skip first 16 minima
+			1:
 			begin
-				flag_next = 1'b0;
-				if (data_ready & uwt_flag[1])
+				if (frame)
 				begin
-					counter_next = counter_reg + 5'd1;
+
+					if (cfg_data[12])
+					begin
+						if (uwt_data > baseline)
+						begin
+							data_next = uwt_data - baseline;
+						end
+						else
+						begin
+							data_next = 12'd0;
+						end
+					end
+					else
+					begin
+						if (uwt_data > cfg_data[11:0])
+						begin
+							data_next = uwt_data - cfg_data[11:0];
+						end
+						else
+						begin
+							data_next = 12'd0;
+						end
+					end
+
+	
+					for(i = 0; i < 31; i = i + 1)
+					begin
+						buffer_next[i+1] = buffer_reg[i] + sample;
+					end
+					buffer_next[0] = sample;
+	
+					good_next = uwt_flag[0] & counter_max;
+
+					// skip first 32 baseline samples
+					// skip 32 samples after peak
 					if (counter_max)
 					begin
-						state_next = 2'd2;
+						if (uwt_flag[0])
+						begin
+							counter_next = 5'd0;
+						end
 					end
-                end
-			end
-
-			2:
-			begin
-				flag_next = 1'b1;
-				if (data_ready)
-				begin
-					if (~counter_max)
+					else
 					begin
 						counter_next = counter_reg + 5'd1;
 					end
-					if (peak_ready_int)
-					begin
-						counter_next = 5'd0;
-					end
-                end
-			end
-
-			default:
-			begin
-				flag_next = 1'b0;
-				state_next = 2'd0;
-				counter_next = 5'd0;
+				end
 			end
 		endcase
 	end
 
-	assign	peak_ready = peak_ready_int;
+	assign ana_good = good_reg;
+	assign ana_data = data_reg;
+	assign ana_base = baseline;
 
 endmodule
Index: unk/MultiChannelUSB/baseline.v
===================================================================
--- /trunk/MultiChannelUSB/baseline.v	(revision 89)
+++ 	(revision )
@@ -1,40 +1,0 @@
-module baseline
-	(
-		input	wire			clk, reset,
-		input	wire			data_ready,
-		input	wire	[1:0]	uwt_flag,
-		input	wire	[11:0]	uwt_data,
-		output	wire	[11:0]	baseline
-	);
-
-	reg		[15:0]	buffer [15:0];
-	wire	[15:0]	sample;
-
-	integer			i;
-
-	assign	sample = {4'd0, uwt_data};
-	
-	always @(posedge clk)
-	begin
-		if (reset)
-		begin
-			for(i = 0; i <= 15; i = i + 1)
-			begin
-				buffer[i] <= 12'd0;
-			end
-		end
-		else
-		begin
-			if (data_ready & uwt_flag[1])
-			begin
-				for(i = 0; i < 15; i = i + 1)
-				begin
-					buffer[i+1] <= buffer[i] + sample;
-				end
-				buffer[0] <= sample;
-			end
-		end
-	end
-
-	assign	baseline = buffer[15][15:4];
-endmodule
Index: /trunk/MultiChannelUSB/configuration.v
===================================================================
--- /trunk/MultiChannelUSB/configuration.v	(revision 90)
+++ /trunk/MultiChannelUSB/configuration.v	(revision 90)
@@ -0,0 +1,91 @@
+module configuration
+	(
+		input	wire			clock, reset,
+
+		input	wire			bus_ssel, bus_wren,
+		input	wire	[3:0]	bus_addr,
+		input	wire	[15:0]	bus_mosi,
+
+		output	wire	[15:0]	bus_miso,
+		output	wire			bus_busy,
+		
+		output  wire	[255:0]	cfg_bits
+	);
+
+	wire 	[15:0]	int_ssel_wire;
+	wire	[15:0]	int_miso_wire;
+	reg		[15:0]	int_miso_reg [3:0];
+
+	wire	[15:0]	int_q_wire [15:0];
+	wire 	[255:0]	int_bits_wire;
+
+	integer i;
+	genvar j;
+
+	generate
+		for (j = 0; j < 16; j = j + 1)
+		begin : BUS_OUTPUT
+			assign int_bits_wire[j*16+15:j*16] = int_q_wire[j];
+			lpm_ff #(
+				.lpm_fftype("DFF"),
+				.lpm_type("LPM_FF"),
+				.lpm_width(16)) cfg_reg_unit (
+				.enable(int_ssel_wire[j] & bus_ssel & bus_wren),
+				.sclr(reset),
+				.clock(clock),
+				.data(bus_mosi),
+				.q(int_q_wire[j]),
+				.aclr(),
+				.aload(),
+				.aset(),
+				.sload(),
+				.sset());
+				end
+	endgenerate
+
+	lpm_mux #(
+		.lpm_size(16),
+		.lpm_type("LPM_MUX"),
+		.lpm_width(16),
+		.lpm_widths(4)) bus_miso_mux_unit (
+		.sel(bus_addr),
+		.data(int_bits_wire),
+		.result(int_miso_wire));
+
+
+	lpm_decode #(
+		.lpm_decodes(16),
+		.lpm_type("LPM_DECODE"),
+		.lpm_width(4)) lpm_decode_unit (
+		.data(bus_addr),
+		.eq(int_ssel_wire),
+		.aclr(),
+		.clken(),
+		.clock(),
+		.enable());
+
+	always @(posedge clock)
+	begin
+		if (reset)
+		begin
+			for(i = 0; i <= 3; i = i + 1)
+			begin
+				int_miso_reg[i] <= 16'd0;
+			end
+		end
+		else
+		begin
+			for(i = 0; i < 3; i = i + 1)
+			begin
+				int_miso_reg[i+1] <= int_miso_reg[i];
+			end
+			int_miso_reg[0] <= int_miso_wire;
+		end
+	end
+
+	// output logic
+	assign	bus_miso = int_miso_reg[3];
+	assign	bus_busy = 1'b0;
+	assign	cfg_bits = int_bits_wire;
+
+endmodule
Index: /trunk/MultiChannelUSB/control.v
===================================================================
--- /trunk/MultiChannelUSB/control.v	(revision 89)
+++ /trunk/MultiChannelUSB/control.v	(revision 90)
@@ -1,37 +1,18 @@
 module control
 	(
-		input	wire			clk,
-
-		output	wire			cfg_reset,
-		input	wire	[15:0]	cfg_src_data,
-		output	wire	[15:0]	cfg_src_addr, cfg_dst_data, cfg_dst_addr,
+		input	wire			clock, reset,
 
 		input	wire			rx_empty, tx_full,
 		input	wire	[7:0]	rx_data,
 
-		input	wire	[1:0]	mux_max_byte,
-		input	wire	[15:0]	mux_min_addr, mux_max_addr,
-		input	wire	[7:0]	mux_q,
-
-		output	wire			mux_reset,
-		output	wire			mux_type,
-		output	wire	[1:0]	mux_chan,
-		output	wire	[1:0]	mux_byte,
-		output	wire	[15:0]	mux_addr,
-
-		output	wire			rx_rdreq,
-		output	wire			tx_wrreq,
+		output	wire			rx_rdreq, tx_wrreq,
 		output	wire	[7:0]	tx_data,
 
-		output	wire			ram_we,
-		output	wire	[19:0]	ram_addr,
-		inout	wire	[17:0]	ram_data,
-
-		input	wire			ept_data_ready,
-		input	wire	[47:0]	ept_data,
-
-		output	wire			i2c_wrreq,
-		output	wire	[15:0]	i2c_data,
-		input	wire			i2c_full,
+		output	wire			bus_wren,
+		output	wire	[31:0]	bus_addr,
+		output	wire	[15:0]	bus_mosi,
+
+		input	wire	[15:0]	bus_miso,
+		input	wire			bus_busy,
 
 		output	wire			led
@@ -39,56 +20,31 @@
 
 	reg		[23:0]	led_counter;
-	reg		[19:0]	ram_counter;	
-	reg		[10:0]	tst_counter;	
-	reg 	[15:0]	int_addr, int_max_addr;
+
+	reg 			int_bus_wren;
+	reg 	[31:0]	int_bus_addr;
+	reg 	[31:0]	int_bus_cntr;
+	reg 	[15:0]	int_bus_mosi;
 
 	reg				int_rdreq, int_wrreq;
-	reg				int_type, int_reset;
-	reg		[1:0]	int_chan, int_byte, int_max_byte;
 	reg		[7:0]	int_data;
 	reg				int_led;
 
-	reg 	[15:0]	int_i2c_data;
-	reg 			int_i2c_wrreq;
-
-	reg		[47:0]	int_ept_data;
-	
-	reg 			int_cfg_reset;
-	reg		[15:0]	int_dst_data, int_dst_addr;
-
-	wire			crc_error = 1'b0;
-	reg				crc_reset;
 	reg		[1:0]	byte_counter;
 	reg		[4:0]	idle_counter;
 
 	reg		[4:0]	state;
-	
-	wire	[15:0]	src, dst;
+
+	reg		[31:0]	address, counter;
+
+	reg		[15:0]	prefix;
+
+	wire	[15:0]	dest, data;
 
 	reg		[7:0]	buffer [3:0];
 
-	assign	src = (buffer[0][7]) ? cfg_src_data : {buffer[2], buffer[3]};
-	assign	dst = {1'b0, buffer[0][6:0], buffer[1]};
-
-	reg				int_ram_we;
-	reg		[17:0]	int_ram_data;
-	wire	[17:0]	int_ram_q;
-	wire	[17:0]	opt_ram_we;
-	assign	ram_we = ~int_ram_we;
-	assign	int_ram_q = ram_data;
-//	assign	ram_data = int_ram_we ? int_ram_data : 18'bz;
-//	assign	ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]};
-	assign	ram_addr = ram_counter;
-
-	genvar j;
-	generate
-		for (j = 0; j < 18; j = j + 1)
-		begin : SRAM_WE
-			assign opt_ram_we[j] = int_ram_we;
-			assign ram_data[j] = opt_ram_we[j] ? int_ram_data[j] : 1'bz;
-		end
-	endgenerate
-
-	always @(posedge clk)
+	assign	dest = {buffer[0], buffer[1]};
+	assign	data = {buffer[2], buffer[3]};
+
+	always @(posedge clock)
 	begin
 		if (~rx_empty)
@@ -114,15 +70,6 @@
 				int_rdreq <= 1'b1;
 				int_wrreq <= 1'b0;
-				int_type <= 1'b0;
-				int_chan <= 2'd0;
-				int_byte <= 2'd0;	
-				int_reset <= 1'b0;
-				crc_reset <= 1'b0;
-				int_ram_we <= 1'b0;
-				int_ram_data <= 16'd0;
-				ram_counter <= 20'd0;
 				idle_counter <= 5'd0;
 				byte_counter <= 2'd0;
-				int_cfg_reset <= 1'b0;
 				state <= 5'd1;
 			end
@@ -130,5 +77,5 @@
 			1: 
 			begin
-				// read 8 bytes
+				// read 4 bytes
 				if (~rx_empty)
 				begin
@@ -148,5 +95,4 @@
 					begin
 						int_rdreq <= 1'b0;
-						crc_reset <= 1'b1;
 						state <= 5'd0;
 					end
@@ -156,86 +102,99 @@
 			2: 
 			begin
-				crc_reset <= 1'b1;
-				if (~crc_error)
-				begin
-					int_dst_addr <= dst;
-					int_dst_data <= src;
-//					memory[dst[3:0]] <= src;
-				
-					case (dst)
-						16'h0000:
-						begin
-							int_cfg_reset <= 1'b1;
-							state <= 5'd0;
-						end
-
-						16'h0001:
-						begin
-							int_type <= src[4];
-							int_chan <= src[1:0];
-							int_reset <= 1'b1;
-							state <= 5'd0;
-						end
-
-						16'h0002:
-						begin
-							int_type <= src[4];
-							int_chan <= src[1:0];
-							state <= 5'd3;
-						end
-
-						16'h0003:
-						begin
-							tst_counter <= 11'd0;	
-							state <= 5'd7;
-						end
-						16'h0004:
-						begin
-							int_ram_we <= 1'b1;
-							int_ram_data <= 18'd0;
-							ram_counter <= 20'd0;	
-							state <= 5'd10;
-						end
-						16'h0005:
-						begin
-							int_i2c_data <= src;
-							int_i2c_wrreq <= 1'b1;
-							state <= 5'd16;
-						end
-						16'h0006:
-						begin
-							int_ram_we <= 1'b1;
-							int_ram_data <= 18'd0;
-							ram_counter <= 20'd0;	
-							state <= 5'd17;
-						end
-
-						default:
-						begin
-							state <= 5'd0;
-						end
-					endcase
-				end
-			end
-
-			// mux transfer
+				case (dest)
+					16'h0000:
+					begin
+						// reset
+						prefix <= 16'd0;
+						state <= 5'd0;
+					end
+
+
+					16'h0001:
+					begin
+						// prefix register
+						prefix <= data;
+						state <= 5'd0;
+					end
+
+
+					16'h0002:
+					begin
+						// address register
+						address <= {prefix, data};
+						prefix <= 16'd0;
+						state <= 5'd0;
+					end
+
+					16'h0003:
+					begin
+						// counter register
+						counter <= {prefix, data};
+						prefix <= 16'd0;
+						state <= 5'd0;
+					end
+
+					16'h0004:
+					begin
+						// single write
+						int_bus_addr <= address;
+						int_bus_mosi <= data;
+						int_bus_wren <= 1'b1;
+						prefix <= 16'd0;
+						state <= 5'd3;
+					end
+
+					16'h0005:
+					begin
+						// multi read
+						int_bus_addr <= address;
+						int_bus_cntr <= counter;
+						int_bus_wren <= 1'b0;
+						prefix <= 16'd0;
+						state <= 5'd4;
+					end
+
+					default:
+					begin
+						prefix <= 16'd0;
+						state <= 5'd0;
+					end
+				endcase
+			end
+
+			// single write
 			3:
 			begin
-				crc_reset <= 1'b0;
-				int_addr <= mux_min_addr;
-				int_max_addr <= mux_min_addr + mux_max_addr;
-				int_max_byte <= mux_max_byte;
-				int_byte <= 2'd0;	
-				state <= 5'd4;
-			end
-	
+				if (~bus_busy)
+				begin
+					int_bus_addr <= 32'd0;
+					int_bus_mosi <= 16'd0;
+					int_bus_wren <= 1'b0;
+					state <= 5'd0;
+				end
+			end
+
+			// multi read
 			4:
 			begin
-				int_wrreq <= 1'b0;
-				state <= 5'd5;
+				if (bus_busy)
+				begin
+					buffer[0] <= 8'd1;
+					buffer[1] <= 8'd0;
+					int_bus_cntr <= 32'd0;
+					state <= 5'd7;
+				end
+				else
+				begin
+					buffer[0] <= 8'd2;
+					buffer[1] <= 8'd0;
+					state <= 5'd6;
+				end
 			end
 
 			5:
 			begin
+				buffer[0] <= bus_miso[7:0];
+				buffer[1] <= bus_miso[15:8];
 				state <= 5'd6;
 			end
@@ -243,207 +202,37 @@
 			6:
 			begin
+				int_bus_addr <= int_bus_addr + 32'd1;
+				state <= 5'd7;
+			end
+
+			7:
+			begin
 				if (~tx_full)
 				begin
-					int_data <= mux_q;
+					int_data <= buffer[0];
 					int_wrreq <= 1'b1;
-					if ((int_byte == int_max_byte) && (int_addr == int_max_addr))
-					begin
-						state <= 5'd0;
+					state <= 5'd8;
+				end
+			end
+
+			8:
+			begin
+				int_data <= buffer[1];
+				state <= 5'd9;
+			end
+
+			9:
+			begin
+				if (~tx_full)
+				begin
+					int_wrreq <= 1'b0;
+					if (|int_bus_cntr)
+					begin
+						state <= 5'd5;
+						int_bus_cntr <= int_bus_cntr - 32'd1;
 					end
 					else
 					begin
-						state <= 5'd4;
-						if (int_byte == int_max_byte)
-						begin
-							int_addr <= int_addr + 16'd1;
-							int_byte <= 2'd0;
-						end
-						else
-						begin
-							int_byte <= int_byte + 2'd1;
-						end
-					end
-				end
-			end
-
-			// tst transfer
-			7:
-			begin
-				crc_reset <= 1'b0;
-				int_data <= tst_counter;
-				int_wrreq <= 1'b1;
-				tst_counter <= tst_counter + 11'd1;
-				state <= 5'd8;
-			end
-			8:
-			begin
-				if (~tx_full)
-				begin
-					int_data <= tst_counter;
-					if (&tst_counter)
-					begin
-						state <= 5'd9;
-					end
-					else
-					begin
-						tst_counter <= tst_counter + 11'd1;
-					end
-				end
-			end
-			9:
-			begin
-				if (~tx_full)
-				begin
-					int_wrreq <= 1'b0;
-					state <= 5'd0;
-				end
-			end
-			// ram transfer
-			10:
-			begin
-				crc_reset <= 1'b0;
-				state <= 5'd11;
-			end
-			11:
-			begin
-				int_ram_data[8:1] <= ram_counter[7:0];
-//				int_ram_data[8:1] <= 8'd0;
-				if (&ram_counter[18:0])
-				begin
-					state <= 5'd12;
-				end
-				else
-				begin
-					state <= 5'd10;
-					ram_counter <= ram_counter + 20'd1;
-				end
-			end
-			12:
-			begin
-				int_ram_we <= 1'b0;
-				int_ram_data <= 18'd0;
-				ram_counter <= 20'd0;
-				state <= 5'd13;
-			end
-			13:
-			begin
-				int_wrreq <= 1'b0;
-				state <= 5'd14;
-			end
-			14:
-			begin
-				state <= 5'd15;
-			end
-			15:
-			begin
-				if (~tx_full)
-				begin
-					int_data <= int_ram_q[8:1];
-					int_wrreq <= 1'b1;
-					if (&ram_counter[18:0])
-					begin
-						state <= 5'd0;
-					end
-					else
-					begin
-						state <= 5'd13;
-						ram_counter <= ram_counter + 20'd1;
-					end
-				end
-			end
-						
-			// i2c write
-			16:
-			begin
-				crc_reset <= 1'b0;
-				if (~i2c_full)
-				begin
-					int_i2c_wrreq <= 1'b0;
-					state <= 5'd0;
-				end
-			end
-
-			// long sample transfer
-			17:
-			begin
-				crc_reset <= 1'b0;
-				if (ept_data_ready)
-				begin
-					ram_counter <= ram_counter + 20'd1;
-					int_ept_data <= ept_data;
-					state <= 5'd18;
-				end
-			end
-			18:
-			begin
-				int_ram_data[8:1] <= int_ept_data[7:0];
-				int_ram_data[17:10] <= int_ept_data[15:8];
-				ram_counter <= ram_counter + 20'd1;
-				state <= 5'd19;
-			end
-			19:
-			begin
-				int_ram_data[8:1] <= int_ept_data[23:16];
-				int_ram_data[17:10] <= int_ept_data[31:24];
-				ram_counter <= ram_counter + 20'd1;
-				state <= 5'd20;
-			end
-
-			20:
-			begin
-				int_ram_data[8:1] <= int_ept_data[39:32];
-				int_ram_data[17:10] <= int_ept_data[47:40];
-				if (&ram_counter)
-				begin
-					int_ram_we <= 1'b0;
-					ram_counter <= 19'd0;
-					state <= 5'd21;
-				end
-				else
-				begin
-					state <= 5'd17;
-				end
-			end
-
-			21:
-			begin
-				int_wrreq <= 1'b0;
-				state <= 5'd22;
-			end
-
-			22:
-			begin
-				state <= 5'd23;
-			end
-
-			23:
-			begin
-				if (~tx_full)
-				begin
-					int_data <= int_ram_q[8:1];
-					int_wrreq <= 1'b1;
-					state <= 5'd24;
-				end
-			end
-
-			24:
-			begin
-				int_data <= int_ram_q[17:10];
-				state <= 5'd25;
-			end
-
-			25:
-			begin
-				if (~tx_full)
-				begin
-					int_wrreq <= 1'b0;
-					if (&ram_counter)
-					begin
-						state <= 5'd0;
-					end
-					else
-					begin
-						state <= 5'd21;
-						ram_counter <= ram_counter + 20'd1;
+						state <= 5'd0;
 					end
 				end
@@ -456,19 +245,11 @@
 		endcase
 	end
-	
-	assign	cfg_reset = int_cfg_reset;
-	assign	cfg_src_addr = {buffer[2], buffer[3]};
-	assign	cfg_dst_data = int_dst_data;
-	assign	cfg_dst_addr = int_dst_addr;
-	assign	mux_reset = int_reset;
-	assign	mux_type = int_type;
-	assign	mux_chan = int_chan;
-	assign	mux_byte = int_byte;
-	assign	mux_addr = int_addr;
+
+	assign	bus_wren = int_bus_wren;
+	assign	bus_addr = int_bus_addr;
+	assign	bus_mosi = int_bus_mosi;
 	assign	rx_rdreq = int_rdreq & (~rx_empty);
 	assign	tx_wrreq = int_wrreq & (~tx_full);
 	assign	tx_data = int_data;
-	assign	i2c_wrreq = int_i2c_wrreq;
-	assign	i2c_data = int_i2c_data;
 	assign	led = int_led;
 
Index: /trunk/MultiChannelUSB/histogram.v
===================================================================
--- /trunk/MultiChannelUSB/histogram.v	(revision 89)
+++ /trunk/MultiChannelUSB/histogram.v	(revision 90)
@@ -1,20 +1,33 @@
 module histogram
-	#(
-		parameter	W	=	32 // bin resolution
-	)
 	(
-		input	wire			clk, reset,
-		input	wire			data_ready,
-		input	wire	[11:0]  data, address,
-		output	wire	[W-1:0]  q
+		input	wire			clock, frame, reset,
+		
+		input	wire	[40:0]  cfg_data,
+		
+		input	wire			hst_good,
+		input	wire	[11:0]  hst_data,
+
+		input	wire			bus_ssel, bus_wren,
+		input	wire	[12:0]	bus_addr,
+		input	wire	[15:0]	bus_mosi,
+
+		output	wire	[15:0]	bus_miso,
+		output	wire			bus_busy
 	);
 	
 	// signal declaration
-	reg		[3:0]	state_reg, state_next;
-	reg				wren_reg, wren_next;
-	reg		[11:0]	addr_reg, addr_next;
-	reg		[W-1:0]	data_reg, data_next;
-
-	wire	[W-1:0]	q_a_wire, q_b_wire;
+	reg		[3:0]	int_case_reg, int_case_next;
+	reg				int_wren_reg, int_wren_next;
+	reg		[11:0]	int_addr_reg, int_addr_next;
+	reg		[31:0]	int_data_reg, int_data_next;
+
+	reg		[12:0]	bus_addr_reg, bus_addr_next;
+	reg		[15:0]	bus_miso_reg, bus_miso_next;
+
+	reg				bus_wren_reg, bus_wren_next;
+	reg		[15:0]	bus_mosi_reg, bus_mosi_next;
+
+	wire	[31:0]	q_a_wire;
+	wire	[15:0]	q_b_wire;
 
 	altsyncram #(
@@ -28,5 +41,5 @@
 		.lpm_type("altsyncram"),
 		.numwords_a(4096),
-		.numwords_b(4096),
+		.numwords_b(8192),
 		.operation_mode("BIDIR_DUAL_PORT"),
 		.outdata_aclr_a("NONE"),
@@ -36,18 +49,20 @@
 		.power_up_uninitialized("FALSE"),
 		.read_during_write_mode_mixed_ports("OLD_DATA"),
+		.read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
+		.read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
 		.widthad_a(12),
-		.widthad_b(12),
-		.width_a(W),
-		.width_b(W),
+		.widthad_b(13),
+		.width_a(32),
+		.width_b(16),
 		.width_byteena_a(1),
 		.width_byteena_b(1),
 		.wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
-		.wren_a(wren_reg),
-		.clock0(clk),
-		.wren_b(1'b0),
-		.address_a(addr_reg),
-		.address_b(address),
-		.data_a(data_reg),
-		.data_b(),
+		.wren_a(int_wren_reg),
+		.clock0(clock),
+		.wren_b(bus_wren_reg),
+		.address_a(int_addr_reg),
+		.address_b(bus_addr_reg),
+		.data_a(int_data_reg),
+		.data_b(bus_mosi_reg),
 		.q_a(q_a_wire),
 		.q_b(q_b_wire),
@@ -68,19 +83,47 @@
 
 	// body
-	always @(posedge clk)
+	always @(posedge clock)
 	begin
 		if (reset)
         begin
-			wren_reg <= 1'b1;
-			addr_reg <= 12'd0;
-			data_reg <= 32'd0;
-			state_reg <= 4'b1;
+			int_wren_reg <= 1'b1;
+			int_addr_reg <= 12'd0;
+			int_data_reg <= 32'd0;
+			int_case_reg <= 4'b1;
+			bus_addr_reg <= 13'd0;
+			bus_miso_reg <= 16'd0;
+			bus_wren_reg <= 1'b0;
+			bus_mosi_reg <= 16'd0;
 		end
 		else
 		begin
-			wren_reg <= wren_next;
-			addr_reg <= addr_next;
-			data_reg <= data_next;
-			state_reg <= state_next;
+			int_wren_reg <= int_wren_next;
+			int_addr_reg <= int_addr_next;
+			int_data_reg <= int_data_next;
+			int_case_reg <= int_case_next;
+			bus_addr_reg <= bus_addr_next;
+			bus_miso_reg <= bus_miso_next;
+			bus_wren_reg <= bus_wren_next;
+			bus_mosi_reg <= bus_mosi_next;
+		end             
+	end
+
+	always @*
+	begin
+		bus_addr_next = bus_addr_reg;
+		bus_miso_next = bus_miso_reg;
+
+		bus_wren_next = 1'b0;
+		bus_mosi_next = bus_mosi_reg;
+
+		if (bus_ssel)
+		begin
+			bus_miso_next = q_b_wire;	
+			bus_addr_next = bus_addr;
+			bus_wren_next = bus_wren;	
+			if (bus_wren)
+			begin
+				bus_mosi_next = bus_mosi;
+			end
 		end
 	end
@@ -88,16 +131,15 @@
 	always @*
 	begin
-		wren_next = wren_reg;
-		addr_next = addr_reg;
-		data_next = data_reg;
-		state_next = state_reg;
-		case (state_reg)
+		int_wren_next = int_wren_reg;
+		int_addr_next = int_addr_reg;
+		int_data_next = int_data_reg;
+		int_case_next = int_case_reg;
+
+		case (int_case_reg)
 			0:
 			begin
-				// nothing to do
-				wren_next = 1'b0;
-				addr_next = 12'd0;
-				data_next = 32'd0;
-				state_next = 4'd0;
+				int_wren_next = 1'b0;
+				int_addr_next = 12'd0;
+				int_data_next = 32'd0;
 			end
 						
@@ -105,12 +147,12 @@
 			begin
 				// write zeros
-				if (&addr_reg)
-				begin
-					wren_next = 1'b0;
-					state_next = 4'd2;
+				if (&int_addr_reg)
+				begin
+					int_wren_next = 1'b0;
+					int_case_next = 4'd2;
 				end
 				else
 				begin
-					addr_next = addr_reg + 12'd1;
+					int_addr_next = int_addr_reg + 12'd1;
 				end
 			end	
@@ -118,9 +160,13 @@
 			2:
 			begin
-				wren_next = 1'b0;
-				if (data_ready)
-				begin
-					addr_next = data;
-					state_next = 4'd3;
+				int_wren_next = 1'b0;
+				if (&int_data_reg)
+				begin
+					int_case_next = 4'd0;
+				end
+				else if (frame & hst_good)
+				begin
+					int_addr_next = hst_data;
+					int_case_next = 4'd3;
 				end
 			end
@@ -128,32 +174,25 @@
 			3:
 			begin
-				state_next = 4'd4;
+				int_case_next = 4'd4;
 			end
 
 			4:
 			begin
-				state_next = 5'd4;
+				int_case_next = 4'd5;
 			end
 
 			5:
 			begin
-				if (&q_a_wire)
-				begin
-					state_next = 4'd0;
-				end
-				else
-				begin
-					wren_next = 1'b1;
-					data_next = q_a_wire + 32'd1;
-					state_next = 4'd2;
-				end
+				int_wren_next = 1'b1;
+				int_data_next = q_a_wire + 32'd1;
+				int_case_next = 4'd2;
 			end
 
 			default:
 			begin
-				wren_next = 1'b0;
-				addr_next = 12'd0;
-				data_next = 32'd0;
-				state_next = 4'd0;
+				int_wren_next = 1'b0;
+				int_addr_next = 12'd0;
+				int_data_next = 32'd0;
+				int_case_next = 4'd0;
 			end
 		endcase
@@ -161,4 +200,5 @@
 
 	// output logic
-	assign	q = q_b_wire;
+	assign	bus_miso = bus_miso_reg;
+	assign	bus_busy = 1'b0;
 endmodule
Index: /trunk/MultiChannelUSB/i2c_fifo.v
===================================================================
--- /trunk/MultiChannelUSB/i2c_fifo.v	(revision 89)
+++ /trunk/MultiChannelUSB/i2c_fifo.v	(revision 90)
@@ -1,8 +1,10 @@
 module i2c_fifo
 	(		
-		input	wire			clk, aclr,
-		input	wire			wrreq,
-		input	wire	[15:0]	data,
-		output	wire			full,
+		input	wire			clock, reset,
+
+		input	wire			bus_ssel, bus_wren,
+		input	wire	[15:0]	bus_mosi,
+
+		output	wire			bus_busy,
 
 		inout	wire			i2c_sda,
@@ -10,8 +12,10 @@
 	);
 
-	wire			int_rdempty, i2c_clk, start, stop;
+	wire			int_rdempty, int_wrfull, i2c_clk, start, stop;
 	wire	[15:0]	int_q;
 
-	reg				int_rdreq, int_clken, int_sdo, int_scl, int_ack;
+	reg				int_bus_busy;
+	reg				int_rdreq, int_wrreq, int_clken, int_sdo, int_scl, int_ack;
+	reg		[15:0]	int_bus_mosi;
 	reg		[15:0]	int_data;
 	reg		[9:0]	counter;
@@ -34,13 +38,13 @@
 		.overflow_checking("ON"),
 		.underflow_checking("ON"),
-		.use_eab("ON")) fifo_tx (
+		.use_eab("OFF")) fifo_tx (
 		.rdreq((~int_rdempty) & (int_rdreq) & (&counter)),
-		.aclr(aclr),
-		.clock(clk),
-		.wrreq(wrreq),
-		.data(data),
+		.aclr(1'b0),
+		.clock(clock),
+		.wrreq(int_wrreq),
+		.data(int_bus_mosi),
 		.empty(int_rdempty),
 		.q(int_q),
-		.full(full),
+		.full(int_wrfull),
 		.almost_empty(),
 		.almost_full(),
@@ -48,5 +52,25 @@
 		.usedw());
 	
-	always @ (posedge clk)
+	always @ (posedge clock)
+	begin
+		int_bus_busy <= int_wrfull;
+
+		if (bus_ssel)
+		begin
+			if (~int_wrfull & bus_wren)
+			begin
+				int_bus_mosi <= bus_mosi;
+				int_wrreq <= 1'b1;
+			end
+		end
+		
+		if (~int_wrfull & int_wrreq)
+		begin
+			int_wrreq <= 1'b0;
+		end
+
+	end
+
+	always @ (posedge clock)
 	begin
 		counter <= counter + 10'd1;
@@ -190,3 +214,6 @@
 	end
 
+	// output logic
+	assign	bus_busy = int_bus_busy;
+
 endmodule
Index: /trunk/MultiChannelUSB/oscilloscope.v
===================================================================
--- /trunk/MultiChannelUSB/oscilloscope.v	(revision 89)
+++ /trunk/MultiChannelUSB/oscilloscope.v	(revision 90)
@@ -1,181 +1,229 @@
 module oscilloscope
 	(
-		input	wire			clk, reset,
-		input	wire			data_ready, trigger,
-		input	wire	[15:0]  data,
-		input	wire	[9:0]	address,
-		output	wire	[9:0]	start_address,
-		output	wire	[15:0]  q
+		input	wire			clock, frame, reset,
+		
+		input	wire	[16:0]  cfg_data,
+
+		input	wire			trg_flag,
+
+		input	wire	[47:0]	osc_data,
+
+		output	wire			ram_wren,
+		output	wire	[19:0]	ram_addr,
+		inout	wire	[17:0]	ram_data,
+
+		input	wire			bus_ssel, bus_wren,
+		input	wire	[19:0]	bus_addr,
+		input	wire	[15:0]	bus_mosi,
+
+		output	wire	[15:0]	bus_miso,
+		output	wire			bus_busy
 	);
-	
-	// signal declaration
-	reg		[3:0]	state_reg, state_next;
-	reg				wren_reg, wren_next;
-	reg		[9:0]	addr_reg, addr_next;
-	reg		[15:0]	data_reg, data_next;
-
-	reg				trig_reg, trig_next;
-	reg		[9:0]	trig_addr_reg, trig_addr_next;
-	reg		[9:0]	counter_reg, counter_next;
-
-	wire	[15:0]	q_wire;
-
-	altsyncram #(
-		.address_reg_b("CLOCK0"),
-		.clock_enable_input_a("BYPASS"),
-		.clock_enable_input_b("BYPASS"),
-		.clock_enable_output_a("BYPASS"),
-		.clock_enable_output_b("BYPASS"),
-		.intended_device_family("Cyclone III"),
-		.lpm_type("altsyncram"),
-		.numwords_a(1024),
-		.numwords_b(1024),
-		.operation_mode("DUAL_PORT"),
-		.outdata_aclr_b("NONE"),
-		.outdata_reg_b("CLOCK0"),
-		.power_up_uninitialized("FALSE"),
-		.read_during_write_mode_mixed_ports("OLD_DATA"),
-		.widthad_a(10),
-		.widthad_b(10),
-		.width_a(16),
-		.width_b(16),
-		.width_byteena_a(1)) osc_ram_unit(
-		.wren_a(wren_reg),
-		.clock0(clk),
-		.address_a(addr_reg),
-		.address_b(address),
-		.data_a(data_reg),
-		.q_b(q_wire),
-		.aclr0(1'b0),
-		.aclr1(1'b0),
-		.addressstall_a(1'b0),
-		.addressstall_b(1'b0),
-		.byteena_a(1'b1),
-		.byteena_b(1'b1),
-		.clock1(1'b1),
-		.clocken0(1'b1),
-		.clocken1(1'b1),
-		.clocken2(1'b1),
-		.clocken3(1'b1),
-		.data_b({16{1'b1}}),
-		.eccstatus(),
-		.q_a(),
-		.rden_a(1'b1),
-		.rden_b(1'b1),
-		.wren_b(1'b0));
-
-	// body
-	always @(posedge clk)
+
+
+	reg		[47:0]	osc_data_reg, osc_data_next;
+
+	reg		[19:0]	cfg_cntr_max_reg, cfg_cntr_max_next;
+	reg		[19:0]	cfg_cntr_mid_reg, cfg_cntr_mid_next;
+
+	reg		[2:0]	int_case_reg, int_case_next;
+
+	reg				int_trig_reg, int_trig_next;
+	reg		[19:0]	int_trig_addr_reg, int_trig_addr_next;
+	reg		[19:0]	int_cntr_reg, int_cntr_next;
+
+	reg		[15:0]	bus_mosi_reg [2:0];
+	reg		[15:0]	bus_mosi_next [2:0];
+
+	reg		[15:0]	bus_miso_reg, bus_miso_next;
+	reg				bus_busy_reg, bus_busy_next;
+
+	reg				ram_wren_reg [2:0];
+	reg				ram_wren_next [2:0];
+
+	reg		[17:0]	ram_data_reg, ram_data_next;
+	reg		[19:0]	ram_addr_reg, ram_addr_next;
+
+	wire	[17:0]	ram_wren_wire;
+
+	assign	ram_wren = ~ram_wren_reg[0];
+	assign	ram_addr = ram_addr_reg;
+
+	integer i;
+	genvar j;
+
+	generate
+		for (j = 0; j < 18; j = j + 1)
+		begin : SRAM_WREN
+			assign ram_wren_wire[j] = ram_wren_reg[2];
+			assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[j] : 1'bz;
+		end
+	endgenerate
+
+	always @(posedge clock)
 	begin
 		if (reset)
-        begin
-			state_reg <= 4'b1;
-			wren_reg <= 1'b1;
-			addr_reg <= 10'd0;
-			data_reg <= 16'd0;
-			trig_reg <= 1'b0;
-			trig_addr_reg <= 10'd0;
-			counter_reg <= 10'd0;
+		begin
+			osc_data_reg <= 48'd0;
+			ram_data_reg <= 18'd0;
+			ram_addr_reg <= 20'd0;
+			bus_miso_reg <= 16'd0;
+			bus_busy_reg <= 1'b0;
+			int_case_reg <= 5'd0;
+			int_cntr_reg <= 20'd0;
+			int_trig_reg <= 1'b0;
+			int_trig_addr_reg <= 20'd0;
+			cfg_cntr_max_reg <= 20'd0;
+			cfg_cntr_mid_reg <= 20'd0;
+			
+			for(i = 0; i <= 2; i = i + 1)
+			begin
+				ram_wren_reg[i] <= 1'b0;
+				bus_mosi_reg[i] <= 16'd0;
+			end
 		end
 		else
 		begin
-			state_reg <= state_next;
-			wren_reg <= wren_next;
-			addr_reg <= addr_next;
-			data_reg <= data_next;
-			trig_reg <= trig_next;
-			trig_addr_reg <= trig_addr_next;
-			counter_reg <= counter_next;
+			osc_data_reg <= osc_data_next;
+			ram_data_reg <= ram_data_next;
+			ram_addr_reg <= ram_addr_next;
+			bus_miso_reg <= bus_miso_next;
+			bus_busy_reg <= bus_busy_next;
+			int_case_reg <= int_case_next;
+			int_cntr_reg <= int_cntr_next;
+			int_trig_reg <= int_trig_next;
+			int_trig_addr_reg <= int_trig_addr_next;
+			cfg_cntr_max_reg <= cfg_cntr_max_next;
+			cfg_cntr_mid_reg <= cfg_cntr_mid_next;
+
+			for(i = 0; i <= 2; i = i + 1)
+			begin
+				ram_wren_reg[i] <= ram_wren_next[i];
+				bus_mosi_reg[i] <= bus_mosi_next[i];
+			end
 		end
 	end
+		
 
 	always @*
 	begin
-		state_next = state_reg;
-		wren_next = wren_reg;
-		addr_next = addr_reg;
-		data_next = data_reg;
-		trig_next = trig_reg;
-		trig_addr_next = trig_addr_reg;
-		counter_next = counter_reg;
-
-		case (state_reg)
+
+		osc_data_next = osc_data_reg;
+		ram_data_next = ram_data_reg;
+		ram_addr_next = ram_addr_reg;
+		bus_miso_next = bus_miso_reg;
+		bus_busy_next = bus_busy_reg;
+		int_case_next = int_case_reg;
+		int_cntr_next = int_cntr_reg;
+		int_trig_next = int_trig_reg;
+		int_trig_addr_next = int_trig_addr_reg;
+		cfg_cntr_max_next = cfg_cntr_max_reg;
+		cfg_cntr_mid_next = cfg_cntr_mid_reg;
+
+		for(i = 0; i < 2; i = i + 1)
+		begin
+			ram_wren_next[i+1] = ram_wren_reg[i];
+			bus_mosi_next[i+1] = bus_mosi_reg[i];
+		end
+		ram_wren_next[0] = 1'b0;
+		bus_mosi_next[0] = 16'd0;
+
+		case (int_case_reg)
 			0:
 			begin
-				// nothing to do 
-				state_next = 4'b0;
-				wren_next = 1'b0;
-				addr_next = 10'd0;
-				data_next = 16'd0;
-				counter_next = 10'd0;
-			end
-			
+				ram_data_next = 18'd0;
+				ram_addr_next = 20'd0;
+				bus_busy_next = 1'b0;
+				int_cntr_next = 20'd0;
+				int_trig_next = 1'b0;
+
+				ram_data_next = {bus_mosi_reg[1][15:8], 1'b0, bus_mosi_reg[1][7:0], 1'b0};
+
+				if (bus_ssel)
+				begin
+					bus_miso_next = {ram_data[17:10], ram_data[8:1]};
+					ram_wren_next[0] = bus_wren;
+					if (bus_wren)
+					begin
+						ram_addr_next = bus_addr;
+						bus_mosi_next[0] = bus_mosi;
+					end
+					else
+					begin
+//						ram_addr_next = int_trig_addr_reg + bus_addr;	
+						ram_addr_next = bus_addr;	
+					end
+				end
+				else if (cfg_data[16])
+				begin
+					// start recording
+					ram_wren_next[0] = 1'b1;
+					bus_busy_next = 1'b1;
+					int_case_next = 3'd1;
+					int_trig_addr_next = 20'd0;
+					cfg_cntr_max_next = {cfg_data[7:0], 10'd0};
+					cfg_cntr_mid_next = {cfg_data[15:8], 10'd0};
+				end
+
+			end
+
+			// sample recording
 			1:
 			begin
-				// write zeros
-				if (&addr_reg)
-				begin
-					wren_next = 1'b0;
-					state_next = 4'd2;
-				end
-				else
-				begin
-					addr_next = addr_reg + 10'd1;
-				end
-			end
-	
+				ram_wren_next[0] = 1'b1;
+				if (frame)
+				begin
+					osc_data_next = osc_data;
+					ram_addr_next = ram_addr_reg + 20'd1;
+					int_case_next = 3'd2;
+
+					if ((~int_trig_reg) & (trg_flag) &
+						(int_cntr_reg == cfg_cntr_mid_reg))
+					begin
+						int_trig_next = 1'b1;
+						int_trig_addr_next = ram_addr_reg;
+					end
+					
+					if (int_trig_reg | (int_cntr_reg < cfg_cntr_mid_reg))
+					begin
+						int_cntr_next = int_cntr_reg + 20'd1;
+					end
+				end
+			end
+
 			2:
 			begin
-				if (data_ready)
-				begin
-					wren_next = 1'b1;
-					data_next = data;
-					state_next = 4'd3;
-				end
+				ram_wren_next[0] = 1'b1;
+				ram_data_next = {osc_data_reg[15:8], 1'b0, osc_data_reg[7:0], 1'b0};
+				ram_addr_next = ram_addr_reg + 20'd1;
+				int_case_next = 3'd3;
 			end
 
 			3:
 			begin
-				// stop write
-				wren_next = 1'b0;
-				addr_next = addr_reg + 10'd1;
-
-				if (&counter_reg)
-				begin
-					state_next = 4'd0;
-				end
-				else
-				begin
-					state_next = 4'd2;
-
-					if ((~trig_reg) & (trigger) 
-						& (counter_reg == 10'd512))
-					begin
-						// trigger
-						trig_next = 1'b1;
-						trig_addr_next = addr_reg;
-					end
-					
-					if (trig_reg | (counter_reg < 10'd512))
-					begin
-						counter_next = counter_reg + 10'd1;
-					end
-				end
-			end
-
-			default:
-			begin
-				state_next = 4'b0;
-				wren_next = 1'b0;
-				addr_next = 10'd0;
-				data_next = 16'd0;
-				counter_next = 10'd0;
-			end
+				ram_wren_next[0] = 1'b1;
+				ram_data_next = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};
+				ram_addr_next = ram_addr_reg + 20'd1;
+				int_case_next = 3'd4;
+			end
+
+			4:
+			begin
+				ram_wren_next[0] = 1'b1;
+				ram_data_next = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
+				int_case_next = 3'd1;
+				if (int_cntr_reg >= cfg_cntr_max_reg)
+				begin
+					ram_wren_next[0] = 1'b0;
+					ram_addr_next = 20'd0;
+					int_case_next = 3'd0;
+				end
+			end
+
 		endcase
 	end
 
-	// output logic
-	assign	q = q_wire;
-	assign	start_address = trig_reg ? (trig_addr_reg ^ 10'h200) + 10'd1: addr_reg + 10'd1;
+	assign bus_miso = bus_miso_reg;
+	assign bus_busy = bus_busy_reg;
 
 endmodule
Index: unk/MultiChannelUSB/pll.v
===================================================================
--- /trunk/MultiChannelUSB/pll.v	(revision 89)
+++ 	(revision )
@@ -1,146 +1,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: pll.v
-// Megafunction Name(s):
-// 			altpll
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 9.0 Build 132 02/25/2009 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2009 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
-//Subscription Agreement, Altera MegaCore Function License 
-//Agreement, or other applicable license agreement, including, 
-//without limitation, that your use is for the sole purpose of 
-//programming logic devices manufactured by Altera and sold by 
-//Altera or its authorized distributors.  Please refer to the 
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll (
-	inclk0,
-	c0);
-
-	input	  inclk0;
-	output	  c0;
-
-	wire [4:0] sub_wire0;
-	wire [0:0] sub_wire4 = 1'h0;
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  sub_wire2 = inclk0;
-	wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
-
-	altpll	altpll_component (
-				.inclk (sub_wire3),
-				.clk (sub_wire0),
-				.activeclock (),
-				.areset (1'b0),
-				.clkbad (),
-				.clkena ({6{1'b1}}),
-				.clkloss (),
-				.clkswitch (1'b0),
-				.configupdate (1'b0),
-				.enable0 (),
-				.enable1 (),
-				.extclk (),
-				.extclkena ({4{1'b1}}),
-				.fbin (1'b1),
-				.fbmimicbidir (),
-				.fbout (),
-				.locked (),
-				.pfdena (1'b1),
-				.phasecounterselect ({4{1'b1}}),
-				.phasedone (),
-				.phasestep (1'b1),
-				.phaseupdown (1'b1),
-				.pllena (1'b1),
-				.scanaclr (1'b0),
-				.scanclk (1'b0),
-				.scanclkena (1'b1),
-				.scandata (1'b0),
-				.scandataout (),
-				.scandone (),
-				.scanread (1'b0),
-				.scanwrite (1'b0),
-				.sclkout0 (),
-				.sclkout1 (),
-				.vcooverrange (),
-				.vcounderrange ());
-	defparam
-		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk0_divide_by = 5,
-		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 2,
-		altpll_component.clk0_phase_shift = "0",
-		altpll_component.compensate_clock = "CLK0",
-		altpll_component.inclk0_input_frequency = 20000,
-		altpll_component.intended_device_family = "Cyclone III",
-		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
-		altpll_component.lpm_type = "altpll",
-		altpll_component.operation_mode = "NORMAL",
-		altpll_component.pll_type = "AUTO",
-		altpll_component.port_activeclock = "PORT_UNUSED",
-		altpll_component.port_areset = "PORT_UNUSED",
-		altpll_component.port_clkbad0 = "PORT_UNUSED",
-		altpll_component.port_clkbad1 = "PORT_UNUSED",
-		altpll_component.port_clkloss = "PORT_UNUSED",
-		altpll_component.port_clkswitch = "PORT_UNUSED",
-		altpll_component.port_configupdate = "PORT_UNUSED",
-		altpll_component.port_fbin = "PORT_UNUSED",
-		altpll_component.port_inclk0 = "PORT_USED",
-		altpll_component.port_inclk1 = "PORT_UNUSED",
-		altpll_component.port_locked = "PORT_UNUSED",
-		altpll_component.port_pfdena = "PORT_UNUSED",
-		altpll_component.port_phasecounterselect = "PORT_UNUSED",
-		altpll_component.port_phasedone = "PORT_UNUSED",
-		altpll_component.port_phasestep = "PORT_UNUSED",
-		altpll_component.port_phaseupdown = "PORT_UNUSED",
-		altpll_component.port_pllena = "PORT_UNUSED",
-		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_UNUSED",
-		altpll_component.port_scanclkena = "PORT_UNUSED",
-		altpll_component.port_scandata = "PORT_UNUSED",
-		altpll_component.port_scandataout = "PORT_UNUSED",
-		altpll_component.port_scandone = "PORT_UNUSED",
-		altpll_component.port_scanread = "PORT_UNUSED",
-		altpll_component.port_scanwrite = "PORT_UNUSED",
-		altpll_component.port_clk0 = "PORT_USED",
-		altpll_component.port_clk1 = "PORT_UNUSED",
-		altpll_component.port_clk2 = "PORT_UNUSED",
-		altpll_component.port_clk3 = "PORT_UNUSED",
-		altpll_component.port_clk4 = "PORT_UNUSED",
-		altpll_component.port_clk5 = "PORT_UNUSED",
-		altpll_component.port_clkena0 = "PORT_UNUSED",
-		altpll_component.port_clkena1 = "PORT_UNUSED",
-		altpll_component.port_clkena2 = "PORT_UNUSED",
-		altpll_component.port_clkena3 = "PORT_UNUSED",
-		altpll_component.port_clkena4 = "PORT_UNUSED",
-		altpll_component.port_clkena5 = "PORT_UNUSED",
-		altpll_component.port_extclk0 = "PORT_UNUSED",
-		altpll_component.port_extclk1 = "PORT_UNUSED",
-		altpll_component.port_extclk2 = "PORT_UNUSED",
-		altpll_component.port_extclk3 = "PORT_UNUSED",
-		altpll_component.width_clock = 5;
-
-
-endmodule
Index: unk/MultiChannelUSB/suppression.v
===================================================================
--- /trunk/MultiChannelUSB/suppression.v	(revision 89)
+++ 	(revision )
@@ -1,25 +1,0 @@
-module suppression
-	(
-		input	wire			clk,
-		input	wire	[11:0]	data,
-		input	wire	[11:0]	baseline,
-		
-		output	wire	[11:0]	result
-	);
-
-	reg		[11:0]	result_int;
-
-	always @(posedge clk)
-	begin
-		if (data > baseline)
-		begin
-			result_int <= data - baseline;
-		end
-		else
-		begin
-			result_int <= 12'd0;
-		end
-	end
-
-	assign	result = result_int;
-endmodule
Index: /trunk/MultiChannelUSB/trigger.v
===================================================================
--- /trunk/MultiChannelUSB/trigger.v	(revision 89)
+++ /trunk/MultiChannelUSB/trigger.v	(revision 90)
@@ -1,25 +1,32 @@
 module trigger
 	(
-		input	wire			clk, reset,
-		input	wire			data_ready,
-		input	wire	[11:0]  data, threshold,
-		output	wire			trigger
+		input	wire			clock, frame, reset,
+		input	wire	[11:0]  cfg_data,
+		input	wire	[11:0]  trg_data,
+		output	wire			trg_flag
 	);
 	
-	reg				int_trigger;
+	reg				trg_flag_reg;
+	reg		[11:0]	cfg_data_reg;
+	reg		[11:0]	trg_data_reg;
 
-	always @(posedge clk)
+	always @(posedge clock)
 	begin
 		if (reset)
         begin
-			int_trigger <= 1'b0;
+			trg_flag_reg <= 1'b0;
         end
-        else if (data_ready)
+        else 
 		begin
-			int_trigger <= (data >= threshold);
+			if (frame)
+			begin
+				cfg_data_reg <= cfg_data;
+				trg_data_reg <= trg_data;
+			end
+			trg_flag_reg <= (trg_data_reg >= cfg_data_reg);
 		end
 	end
 	
-	assign trigger = int_trigger;
+	assign trg_flag = trg_flag_reg;
 
 endmodule
Index: /trunk/MultiChannelUSB/usb_fifo.v
===================================================================
--- /trunk/MultiChannelUSB/usb_fifo.v	(revision 89)
+++ /trunk/MultiChannelUSB/usb_fifo.v	(revision 90)
@@ -7,5 +7,5 @@
 		output	wire	[1:0]	usb_addr,
 		
-		input	wire			clk, aclr,
+		input	wire			clk,
 		input	wire			tx_wrreq, rx_rdreq,
 		input	wire	[7:0]	tx_data,
@@ -35,7 +35,7 @@
 		.overflow_checking("ON"),
 		.underflow_checking("ON"),
-		.use_eab("ON"),
+		.use_eab("OFF"),
 		.write_aclr_synch("OFF")) fifo_tx (
-		.aclr(aclr),
+		.aclr(1'b0),
 		.data(tx_data),
 		.rdclk(usb_clk),
@@ -62,7 +62,7 @@
 		.overflow_checking("ON"),
 		.underflow_checking("ON"),
-		.use_eab("ON"),
+		.use_eab("OFF"),
 		.write_aclr_synch("OFF")) fifo_rx (
-		.aclr(aclr),
+		.aclr(1'b0),
 		.data(int_rx_data),
 		.rdclk(clk),
Index: /trunk/MultiChannelUSB/uwt_bior31.v
===================================================================
--- /trunk/MultiChannelUSB/uwt_bior31.v	(revision 89)
+++ /trunk/MultiChannelUSB/uwt_bior31.v	(revision 90)
@@ -4,6 +4,5 @@
 	)
 	(
-		input	wire			clk, reset,
-		input	wire			data_ready,
+		input	wire			clock, frame, reset,
 		input	wire	[31:0]	x,
 		output	wire	[31:0]	d,
@@ -37,5 +36,5 @@
 	integer			i;
 	
-	always @(posedge clk)
+	always @(posedge clock)
 	begin
 		if (reset)
@@ -55,5 +54,5 @@
 			end
 		end
-		else if (data_ready)
+		else if (frame)
 		begin
 			d_reg <= d_next;