Index: trunk/MultiChannelUSB/Paella.v
===================================================================
--- trunk/MultiChannelUSB/Paella.v	(revision 85)
+++ trunk/MultiChannelUSB/Paella.v	(revision 86)
@@ -149,16 +149,11 @@
 	reg 	[15:0]	mux_min_addr, mux_max_addr;
 
-	wire			adc_clk [N-1:0];
 	wire 	[11:0]	adc_data [N-1:0];
 
-	wire			data_ready [N-1:0];
+	wire			data_ready;
     wire	[11:0]	data [N-1:0];
     wire	[11:0]	int_data [N-1:0];
 
-    wire			cmp_data_ready;
     wire	[11:0]	cmp_data;
-
-    wire			ept_data_ready;
-    wire	[47:0]	ept_data;
     
 	wire	[11:0]	nowhere;
@@ -166,11 +161,4 @@
 	wire			sys_clk;
 
-
-/*
-    assign	osc_thrs[0] = 16'd40;
-    assign	osc_thrs[1] = 16'd60;
-    assign	osc_thrs[2] = 16'd40;
-    assign	osc_thrs[3] = 16'd1650;
-*/
 	wire 	[31:0]	uwt_d1 [N-1:0];
 	wire 	[31:0]	uwt_a1 [N-1:0];
@@ -187,12 +175,4 @@
 	wire 	[1:0]	uwt_flag3 [N-1:0];
 
-	assign	adc_clk[0] = ADC_FCO;
-	assign	adc_clk[1] = ADC_FCO;
-	assign	adc_clk[2] = ADC_FCO;
-
-/*    
-    assign	adc_clk[2] = CON_CCLK[0];
-    assign	adc_data[2] = CON_C[11:0];
-*/
 /*
 	adc_para adc_para_unit (
@@ -219,5 +199,4 @@
 		.data(adc_data[2]));
 //		.data(nowhere);
-
 
 	adc_lvds #(
@@ -232,5 +211,4 @@
 					adc_data[1],
 					adc_data[0] }));
-
 
 	reg		[15:0]	cfg_memory [31:0];
@@ -262,13 +240,10 @@
 	end
 
-	assign ept_data_ready = cmp_data_ready & data_ready[2] & data_ready[1] & data_ready[0];
-	assign ept_data = {cmp_data, int_data[2], int_data[1], int_data[0]};
-
-	adc_fifo cmp_fifo_unit (
+	adc_fifo #(.W(48)) adc_fifo_unit (
 		.adc_clk(ADC_FCO),
-		.adc_data(CON_B[11:0]),
+		.adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),
 		.clk(sys_clk),
-		.data_ready(cmp_data_ready),
-		.data(cmp_data));
+		.data_ready(data_ready),
+		.data({cmp_data, int_data[2], int_data[1], int_data[0]}));
 
 	genvar i;
@@ -289,16 +264,9 @@
 			assign bln_mux_sel[i] = cfg_memory[23+i][7:4];
 
-			adc_fifo adc_fifo_unit (
-				.adc_clk(adc_clk[i]),
-				.adc_data(adc_data[i]),
-				.clk(sys_clk),
-				.data_ready(data_ready[i]),
-				.data(int_data[i]));
-
 			assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
 
 			uwt_bior31 #(.L(1)) uwt_1_unit (
 				.clk(sys_clk),
-				.data_ready(data_ready[i]),
+				.data_ready(data_ready),
 				.x({20'h00000, data[i]}),
 				.d(uwt_d1[i]),
@@ -309,5 +277,5 @@
 			uwt_bior31 #(.L(2)) uwt_2_unit (
 				.clk(sys_clk),
-				.data_ready(data_ready[i]),
+				.data_ready(data_ready),
 				.x(uwt_a1[i]),
 				.d(uwt_d2[i]),
@@ -318,5 +286,5 @@
 			uwt_bior31 #(.L(3)) uwt_3_unit (
 				.clk(sys_clk),
-				.data_ready(data_ready[i]),
+				.data_ready(data_ready),
 				.x(uwt_a2[i]),
 				.d(uwt_d3[i]),
@@ -364,5 +332,5 @@
 				.sel(hst_mux_sel[i][0]),
 				.data({	{uwt_peak3[i][11:0], ana_peak_ready[i]},
-						{data[i], data_ready[i]} }),
+						{data[i], data_ready} }),
 				.result(hst_mux_data[i]));
 	
@@ -379,5 +347,5 @@
 				.clk(sys_clk),
 				.reset(bln_reset[i]),
-				.data_ready(data_ready[i]),
+				.data_ready(data_ready),
 				.uwt_flag(uwt_flag3[i]),
 				.uwt_data(uwt_peak3[i]),
@@ -387,5 +355,5 @@
 				.clk(sys_clk),
 				.reset(ana_reset[i]),
-				.data_ready(data_ready[i]),
+				.data_ready(data_ready),
 				.uwt_flag(uwt_flag3[i]),
 				.peak_ready(ana_peak_ready[i]),
@@ -411,5 +379,5 @@
 				.clk(sys_clk),
 				.reset(trg_reset[i]),
-				.data_ready(data_ready[i]),
+				.data_ready(data_ready),
 				.data(trg_mux_data[i]),
 				.threshold(cfg_trg_threshold[i]),
@@ -420,5 +388,5 @@
 				.clk(sys_clk),
 				.reset(osc_reset[i]),
-				.data_ready(data_ready[i]),
+				.data_ready(data_ready),
 				.data(osc_mux_data[i]),
 				.trigger(osc_trig[i]),
@@ -440,7 +408,5 @@
 
 		case(mux_type)
-//		case({mux_type, mux_chan})
 			1'b0:
-//			3'b000, 3'b001, 3'b010, 3'b011:
 			begin
 				osc_reset[mux_chan] = mux_reset;
@@ -452,5 +418,4 @@
 
 			1'b1:
-//			3'b100, 3'b101, 3'b110, 3'b011:
 			begin
 				hst_reset[mux_chan] = mux_reset;
@@ -524,6 +489,6 @@
 		.ram_addr(RAM_ADDR),
 		.ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
-		.ept_data_ready(ept_data_ready),
-		.ept_data(ept_data),
+		.ept_data_ready(data_ready),
+		.ept_data({cmp_data, data[2], data[1], data[0]}),
 		.i2c_wrreq(i2c_wrreq),
 		.i2c_data(i2c_data),
Index: trunk/MultiChannelUSB/adc_fifo.v
===================================================================
--- trunk/MultiChannelUSB/adc_fifo.v	(revision 85)
+++ trunk/MultiChannelUSB/adc_fifo.v	(revision 86)
@@ -1,17 +1,19 @@
 module adc_fifo
+	#(
+		parameter	W	=	48 // fifo width
+	)
 	(
 		input	wire			adc_clk,
-		input	wire	[11:0]	adc_data,
+		input	wire	[W-1:0]	adc_data,
 
 		input	wire			clk,
 		output	wire			data_ready,
-		output	wire	[11:0]	data
+		output	wire	[W-1:0]	data
 	);
 
-	wire	[11:0]	int_q;
-	reg		[11:0]	int_data;
+	wire	[W-1:0]	int_q;
+	reg		[W-1:0]	int_data;
 	
-	reg		[1:0]	state;
-	reg				int_rdreq, int_data_ready;
+	reg				state, int_rdreq, int_data_ready;
 	wire			int_wrfull, int_rdempty;
 
@@ -21,5 +23,5 @@
 		.lpm_showahead("ON"),
 		.lpm_type("dcfifo"),
-		.lpm_width(12),
+		.lpm_width(W),
 		.lpm_widthu(4),
 		.rdsync_delaypipe(4),
@@ -46,12 +48,12 @@
 	begin
 		case (state)
-			2'd0:
+			1'b0:
 			begin
 				int_rdreq <= 1'b1;
 				int_data_ready <= 1'b0;
-				state <= 2'd1;
+				state <= 1'b1;
 			end
 
-			2'd1: 
+			1'b1: 
 			begin
 				if (~int_rdempty)
@@ -60,19 +62,7 @@
 					int_rdreq <= 1'b0;
 					int_data_ready <= 1'b1;
-					state <= 2'd0;
+					state <= 1'b0;
 				end
 			end
-
-			2'd2:
-			begin
-				int_data_ready <= 1'b0;
-				state <= 2'd3;
-			end
-
-			2'd3:
-			begin
-				state <= 2'd0;
-			end
-
 		endcase
 	end