Index: trunk/MultiChannelUSB/control.v
===================================================================
--- trunk/MultiChannelUSB/control.v	(revision 79)
+++ trunk/MultiChannelUSB/control.v	(revision 84)
@@ -28,4 +28,7 @@
 		inout	wire	[17:0]	ram_data,
 
+		input	wire			ept_data_ready,
+		input	wire	[47:0]	ept_data,
+
 		output	wire			i2c_wrreq,
 		output	wire	[15:0]	i2c_data,
@@ -36,5 +39,5 @@
 
 	reg		[23:0]	led_counter;
-	reg		[18:0]	ram_counter;	
+	reg		[19:0]	ram_counter;	
 	reg		[10:0]	tst_counter;	
 	reg 	[15:0]	int_addr, int_max_addr;
@@ -49,4 +52,6 @@
 	reg 			int_i2c_wrreq;
 
+	reg		[47:0]	int_ept_data;
+	
 	reg 			int_cfg_reset;
 	reg		[15:0]	int_dst_data, int_dst_addr;
@@ -74,5 +79,5 @@
 //	assign	ram_data = int_ram_we ? int_ram_data : 18'bz;
 //	assign	ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]};
-	assign	ram_addr = {1'd0, ram_counter[18:0]};
+	assign	ram_addr = ram_counter;
 
 	genvar j;
@@ -116,5 +121,5 @@
 				int_ram_we <= 1'b0;
 				int_ram_data <= 16'd0;
-				ram_counter <= 19'd0;
+				ram_counter <= 20'd0;
 				idle_counter <= 5'd0;
 				byte_counter <= 2'd0;
@@ -183,5 +188,5 @@
 						begin
 							tst_counter <= 11'd0;	
-							state <= 5'd6;
+							state <= 5'd7;
 						end
 						16'h0004:
@@ -189,6 +194,6 @@
 							int_ram_we <= 1'b1;
 							int_ram_data <= 18'd0;
-							ram_counter <= 19'd0;	
-							state <= 5'd9;
+							ram_counter <= 20'd0;	
+							state <= 5'd10;
 						end
 						16'h0005:
@@ -196,5 +201,12 @@
 							int_i2c_data <= src;
 							int_i2c_wrreq <= 1'b1;
-							state <= 5'd15;
+							state <= 5'd16;
+						end
+						16'h0006:
+						begin
+							int_ram_we <= 1'b1;
+							int_ram_data <= 18'd0;
+							ram_counter <= 20'd0;	
+							state <= 5'd17;
 						end
 
@@ -226,4 +238,9 @@
 			5:
 			begin
+				state <= 5'd6;
+			end
+
+			6:
+			begin
 				if (~tx_full)
 				begin
@@ -251,5 +268,5 @@
 
 			// tst transfer
-			6:
+			7:
 			begin
 				crc_reset <= 1'b0;
@@ -257,7 +274,7 @@
 				int_wrreq <= 1'b1;
 				tst_counter <= tst_counter + 11'd1;
-				state <= 5'd7;
-			end
-			7:
+				state <= 5'd8;
+			end
+			8:
 			begin
 				if (~tx_full)
@@ -266,5 +283,5 @@
 					if (&tst_counter)
 					begin
-						state <= 5'd8;
+						state <= 5'd9;
 					end
 					else
@@ -274,5 +291,5 @@
 				end
 			end
-			8:
+			9:
 			begin
 				if (~tx_full)
@@ -283,40 +300,126 @@
 			end
 			// ram transfer
-			9:
+			10:
 			begin
 				crc_reset <= 1'b0;
-				state <= 5'd10;
-			end
-			10:
+				state <= 5'd11;
+			end
+			11:
 			begin
 				int_ram_data[8:1] <= ram_counter[7:0];
 //				int_ram_data[8:1] <= 8'd0;
-				if (&ram_counter)
-				begin
-					state <= 5'd11;
+				if (&ram_counter[18:0])
+				begin
+					state <= 5'd12;
 				end
 				else
 				begin
-					state <= 5'd9;
-					ram_counter <= ram_counter + 19'd1;
-				end
-			end
-			11:
+					state <= 5'd10;
+					ram_counter <= ram_counter + 20'd1;
+				end
+			end
+			12:
 			begin
 				int_ram_we <= 1'b0;
 				int_ram_data <= 18'd0;
-				ram_counter <= 19'd0;
-				state <= 5'd12;
-			end
-			12:
+				ram_counter <= 20'd0;
+				state <= 5'd13;
+			end
+			13:
 			begin
 				int_wrreq <= 1'b0;
-				state <= 5'd13;
-			end
-			13:
-			begin
 				state <= 5'd14;
 			end
 			14:
+			begin
+				state <= 5'd15;
+			end
+			15:
+			begin
+				if (~tx_full)
+				begin
+					int_data <= int_ram_q[8:1];
+					int_wrreq <= 1'b1;
+					if (&ram_counter[18:0])
+					begin
+						state <= 5'd0;
+					end
+					else
+					begin
+						state <= 5'd13;
+						ram_counter <= ram_counter + 20'd1;
+					end
+				end
+			end
+						
+			// i2c write
+			16:
+			begin
+				crc_reset <= 1'b0;
+				if (~i2c_full)
+				begin
+					int_i2c_wrreq <= 1'b0;
+					state <= 5'd0;
+				end
+			end
+
+			// long sample transfer
+			17:
+			begin
+				crc_reset <= 1'b0;
+				if (ept_data_ready)
+				begin
+					ram_counter <= ram_counter + 20'd1;
+					int_ept_data <= ept_data;
+					state <= 5'd18;
+				end
+			end
+			18:
+			begin
+//				int_ram_data[8:1] <= ram_counter[7:0];
+				int_ram_data[8:1] <= int_ept_data[7:0];
+				int_ram_data[17:10] <= int_ept_data[15:8];
+				ram_counter <= ram_counter + 20'd1;
+				state <= 5'd19;
+			end
+			19:
+			begin
+//				int_ram_data[8:1] <= ram_counter[7:0];
+				int_ram_data[8:1] <= int_ept_data[23:16];
+				int_ram_data[17:10] <= int_ept_data[31:24];
+				ram_counter <= ram_counter + 20'd1;
+				state <= 5'd20;
+			end
+
+			20:
+			begin
+//				int_ram_data[8:1] <= ram_counter[7:0];
+				int_ram_data[8:1] <= int_ept_data[39:32];
+				int_ram_data[17:10] <= int_ept_data[47:40];
+				if (&ram_counter)
+				begin
+					int_ram_we <= 1'b0;
+					int_ram_data <= 18'd0;
+					ram_counter <= 19'd0;
+					state <= 5'd21;
+				end
+				else
+				begin
+					state <= 5'd17;
+				end
+			end
+/*
+			21:
+			begin
+				int_wrreq <= 1'b0;
+				state <= 5'd22;
+			end
+
+			22:
+			begin
+				state <= 5'd23;
+			end
+
+			23:
 			begin
 				if (~tx_full)
@@ -330,18 +433,51 @@
 					else
 					begin
-						state <= 5'd12;
-						ram_counter <= ram_counter + 19'd1;
-					end
-				end
-			end
-						
-			// i2c write
-			15:
-			begin
-				crc_reset <= 1'b0;
-				if (~i2c_full)
-				begin
-					int_i2c_wrreq <= 1'b0;
-					state <= 5'd0;
+						state <= 5'd21;
+						ram_counter <= ram_counter + 20'd1;
+					end
+				end
+			end
+*/
+			21:
+			begin
+				int_wrreq <= 1'b0;
+				state <= 5'd22;
+			end
+
+			22:
+			begin
+				state <= 5'd23;
+			end
+
+			23:
+			begin
+				if (~tx_full)
+				begin
+					int_data <= int_ram_q[8:1];
+					int_wrreq <= 1'b1;
+					state <= 5'd24;
+				end
+			end
+
+			24:
+			begin
+				int_data <= int_ram_q[17:10];
+				state <= 5'd25;
+			end
+
+			25:
+			begin
+				if (~tx_full)
+				begin
+					int_wrreq <= 1'b0;
+					if (&ram_counter)
+					begin
+						state <= 5'd0;
+					end
+					else
+					begin
+						state <= 5'd21;
+						ram_counter <= ram_counter + 20'd1;
+					end
 				end
 			end
