Index: /trunk/MultiChannelUSB/Paella.qsf =================================================================== --- /trunk/MultiChannelUSB/Paella.qsf (revision 83) +++ /trunk/MultiChannelUSB/Paella.qsf (revision 84) @@ -59,4 +59,5 @@ set_global_assignment -name VERILOG_FILE histogram.v set_global_assignment -name VERILOG_FILE trigger.v +set_global_assignment -name VERILOG_FILE suppression.v set_global_assignment -name VERILOG_FILE oscilloscope.v set_global_assignment -name VERILOG_FILE usb_fifo.v @@ -65,4 +66,5 @@ set_global_assignment -name VERILOG_FILE test.v set_global_assignment -name VERILOG_FILE test_pll.v +set_global_assignment -name VERILOG_FILE sys_pll.v set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF set_global_assignment -name ENABLE_CLOCK_LATENCY ON Index: /trunk/MultiChannelUSB/Paella.v =================================================================== --- /trunk/MultiChannelUSB/Paella.v (revision 83) +++ /trunk/MultiChannelUSB/Paella.v (revision 84) @@ -8,5 +8,5 @@ inout wire I2C_SCL, inout wire [4:0] CON_A, - inout wire [15:0] CON_B, + input wire [15:0] CON_B, input wire [12:0] CON_C, input wire [1:0] CON_BCLK, @@ -52,5 +52,5 @@ assign RAM_ADDR = 20'h00000; */ - assign RAM_CLK = CLK_50MHz; + assign RAM_CLK = sys_clk; assign RAM_CE1 = 1'b0; @@ -58,5 +58,4 @@ assign TRG = 4'bz; assign CON_A = 5'bz; - assign CON_B = 16'bz; assign USB_PA0 = 1'bz; assign USB_PA1 = 1'bz; @@ -95,5 +94,5 @@ .usb_addr(usb_addr), - .clk(CLK_50MHz), + .clk(sys_clk), .aclr(usb_aclr), @@ -106,5 +105,5 @@ .rx_q(usb_rx_data) ); - + reg bln_reset [N-1:0]; wire [11:0] baseline [N-1:0]; @@ -113,4 +112,5 @@ reg ana_reset [N-1:0]; wire ana_peak_ready [N-1:0]; + wire ana_peak_debug [N-1:0]; reg osc_reset [N-1:0]; @@ -155,5 +155,16 @@ wire [11:0] data [N-1:0]; wire [11:0] int_data [N-1:0]; + + wire cmp_data_ready; + wire [11:0] cmp_data; + + wire ept_data_ready; + wire [47:0] ept_data; + wire [11:0] nowhere; + + wire sys_clk; + + /* assign osc_thrs[0] = 16'd40; @@ -176,7 +187,7 @@ wire [1:0] uwt_flag3 [N-1:0]; - assign adc_clk[0] = ADC_FCO; - assign adc_clk[1] = ADC_FCO; - assign adc_clk[2] = ADC_FCO; + assign adc_clk[0] = ADC_FCO; + assign adc_clk[1] = ADC_FCO; + assign adc_clk[2] = ADC_FCO; /* @@ -199,29 +210,14 @@ .c0(adc_pll_clk)); */ -/* - wire tst_adc_clk; - wire [11:0] tst_adc_data; + + sys_pll sys_pll_unit( + .inclk0(CLK_50MHz), + .c0(sys_clk)); test test_unit( - .clk(CLK_50MHz), - .tst_clk(tst_adc_clk), - .tst_data(tst_adc_data)); - - assign adc_clk[2] = tst_adc_clk; - assign adc_data[2] = tst_adc_data; -*/ -/* - altserial_flash_loader #( - .enable_shared_access("OFF"), - .enhanced_mode(1), - .intended_device_family("Cyclone III")) sfl_unit ( - .noe(1'b0), - .asmi_access_granted(), - .asmi_access_request(), - .data0out(), - .dclkin(), - .scein(), - .sdoin()); -*/ + .clk(ADC_FCO), + .data(adc_data[2])); +// .data(nowhere); + adc_lvds #( @@ -232,5 +228,6 @@ .lvds_fco(ADC_FCO), .lvds_d(ADC_D[2:0]), - .adc_data({ adc_data[2], +// .adc_data({ adc_data[2], + .adc_data({ nowhere, adc_data[1], adc_data[0] })); @@ -250,5 +247,5 @@ integer j; - always @(posedge CLK_50MHz) + always @(posedge sys_clk) begin if (cfg_reset) @@ -265,4 +262,14 @@ end + assign ept_data_ready = cmp_data_ready & data_ready[2] & data_ready[1] & data_ready[0]; + assign ept_data = {cmp_data, int_data[2], int_data[1], int_data[0]}; + + adc_fifo cmp_fifo_unit ( + .adc_clk(ADC_FCO), + .adc_data(CON_B[11:0]), + .clk(sys_clk), + .data_ready(cmp_data_ready), + .data(cmp_data)); + genvar i; @@ -285,5 +292,5 @@ .adc_clk(adc_clk[i]), .adc_data(adc_data[i]), - .clk(CLK_50MHz), + .clk(sys_clk), .data_ready(data_ready[i]), .data(int_data[i])); @@ -292,5 +299,5 @@ uwt_bior31 #(.L(1)) uwt_1_unit ( - .clk(CLK_50MHz), + .clk(sys_clk), .data_ready(data_ready[i]), .x({20'h00000, data[i]}), @@ -301,5 +308,5 @@ uwt_bior31 #(.L(2)) uwt_2_unit ( - .clk(CLK_50MHz), + .clk(sys_clk), .data_ready(data_ready[i]), .x(uwt_a1[i]), @@ -310,5 +317,5 @@ uwt_bior31 #(.L(3)) uwt_3_unit ( - .clk(CLK_50MHz), + .clk(sys_clk), .data_ready(data_ready[i]), .x(uwt_a2[i]), @@ -319,10 +326,13 @@ lpm_mux #( - .lpm_size(5), + .lpm_size(7), .lpm_type("LPM_MUX"), .lpm_width(12), .lpm_widths(3)) osc_mux_unit ( .sel(osc_mux_sel[i][2:0]), - .data({ bln_baseline[i], + .data({ {ana_peak_debug[i], 11'd0}, + hst_data[i], +// uwt_d3[i][11:0], + bln_baseline[i], uwt_a3[i][20:9], uwt_a2[i][17:6], @@ -332,10 +342,13 @@ lpm_mux #( - .lpm_size(5), + .lpm_size(7), .lpm_type("LPM_MUX"), .lpm_width(12), .lpm_widths(3)) trg_mux_unit ( .sel(trg_mux_sel[i][2:0]), - .data({ bln_baseline[i], + .data({ {ana_peak_ready[i], 11'd0}, + hst_data[i], +// uwt_d3[i][11:0], + bln_baseline[i], uwt_a3[i][20:9], uwt_a2[i][17:6], @@ -364,5 +377,5 @@ baseline baseline_unit ( - .clk(CLK_50MHz), + .clk(sys_clk), .reset(bln_reset[i]), .data_ready(data_ready[i]), @@ -372,15 +385,21 @@ analyser analyser_unit ( - .clk(CLK_50MHz), + .clk(sys_clk), .reset(ana_reset[i]), .data_ready(data_ready[i]), .uwt_flag(uwt_flag3[i]), - .peak_ready(ana_peak_ready[i])); - - assign hst_data[i] = (hst_mux_data[i][12:1] > bln_mux_data[i]) ? (hst_mux_data[i][12:1] - bln_mux_data[i]) : 12'd0; + .peak_ready(ana_peak_ready[i]), + .peak_debug(ana_peak_debug[i])); + + suppression suppression_unit ( + .clk(sys_clk), + .data(hst_mux_data[i][12:1]), + .baseline(bln_mux_data[i]), + .result(hst_data[i])); + assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]); histogram #(.W(32)) histogram_unit ( - .clk(CLK_50MHz), + .clk(sys_clk), .reset(hst_reset[i]), .data_ready(hst_data_ready[i]), @@ -390,5 +409,5 @@ trigger trigger_unit ( - .clk(CLK_50MHz), + .clk(sys_clk), .reset(trg_reset[i]), .data_ready(data_ready[i]), @@ -399,5 +418,5 @@ oscilloscope oscilloscope_unit ( - .clk(CLK_50MHz), + .clk(sys_clk), .reset(osc_reset[i]), .data_ready(data_ready[i]), @@ -465,5 +484,5 @@ i2c_fifo i2c_unit( - .clk(CLK_50MHz), + .clk(sys_clk), .aclr(i2c_aclr), .wrreq(i2c_wrreq), @@ -481,5 +500,5 @@ control control_unit ( - .clk(CLK_50MHz), + .clk(sys_clk), .cfg_reset(cfg_reset), .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]), @@ -505,4 +524,6 @@ .ram_addr(RAM_ADDR), .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}), + .ept_data_ready(ept_data_ready), + .ept_data(ept_data), .i2c_wrreq(i2c_wrreq), .i2c_data(i2c_data), @@ -510,3 +531,17 @@ .led(LED)); +/* + altserial_flash_loader #( + .enable_shared_access("OFF"), + .enhanced_mode(1), + .intended_device_family("Cyclone III")) sfl_unit ( + .noe(1'b0), + .asmi_access_granted(), + .asmi_access_request(), + .data0out(), + .dclkin(), + .scein(), + .sdoin()); +*/ + endmodule Index: /trunk/MultiChannelUSB/adc_fifo.v =================================================================== --- /trunk/MultiChannelUSB/adc_fifo.v (revision 83) +++ /trunk/MultiChannelUSB/adc_fifo.v (revision 84) @@ -12,5 +12,6 @@ reg [11:0] int_data; - reg state, int_rdreq, int_data_ready; + reg [1:0] state; + reg int_rdreq, int_data_ready; wire int_wrfull, int_rdempty; @@ -26,5 +27,5 @@ .overflow_checking("ON"), .underflow_checking("ON"), - .use_eab("OFF"), + .use_eab("ON"), .write_aclr_synch("OFF")) fifo_unit ( .aclr(1'b0), @@ -45,12 +46,12 @@ begin case (state) - 1'b0: + 2'd0: begin int_rdreq <= 1'b1; int_data_ready <= 1'b0; - state <= 1'b1; + state <= 2'd1; end - 1'b1: + 2'd1: begin if (~int_rdempty) @@ -59,14 +60,19 @@ int_rdreq <= 1'b0; int_data_ready <= 1'b1; - state <= 1'b0; + state <= 2'd0; end end - default: + 2'd2: begin - int_rdreq <= 1'b1; int_data_ready <= 1'b0; - state <= 1'b1; + state <= 2'd3; end + + 2'd3: + begin + state <= 2'd0; + end + endcase end Index: /trunk/MultiChannelUSB/analyser.v =================================================================== --- /trunk/MultiChannelUSB/analyser.v (revision 83) +++ /trunk/MultiChannelUSB/analyser.v (revision 84) @@ -4,12 +4,15 @@ input wire data_ready, input wire [1:0] uwt_flag, - output wire peak_ready + output wire peak_ready, + output wire peak_debug ); + reg flag_reg, flag_next; reg [1:0] state_reg, state_next; - reg [3:0] counter_reg, counter_next; - reg peak_ready_reg, peak_ready_next; + reg [4:0] counter_reg, counter_next; + reg peak_ready_reg; wire counter_max = (&counter_reg); + wire peak_ready_int = (flag_reg & data_ready & uwt_flag[0] & counter_max); always @(posedge clk) @@ -17,13 +20,15 @@ if (reset) begin + flag_reg <= 1'b0; state_reg <= 2'd0; - counter_reg <= 4'd0; + counter_reg <= 5'd0; peak_ready_reg <= 1'b0; end else begin + flag_reg <= flag_next; state_reg <= state_next; counter_reg <= counter_next; - peak_ready_reg <= peak_ready_next; + peak_ready_reg <= peak_ready_int; end end @@ -31,14 +36,14 @@ always @* begin + flag_next = flag_reg; state_next = state_reg; counter_next = counter_reg; - peak_ready_next = peak_ready_reg; case (state_reg) 0: // skip first 16 samples begin - peak_ready_next = 1'b0; + flag_next = 1'b0; if (data_ready) begin - counter_next = counter_reg + 4'd1; + counter_next = counter_reg + 5'd1; if (counter_max) begin @@ -50,7 +55,8 @@ 1: // skip first 16 minima begin + flag_next = 1'b0; if (data_ready & uwt_flag[1]) begin - counter_next = counter_reg + 4'd1; + counter_next = counter_reg + 5'd1; if (counter_max) begin @@ -62,28 +68,28 @@ 2: begin - if (data_ready & uwt_flag[0] & counter_max) + flag_next = 1'b1; + if (data_ready) begin - counter_next = 4'd0; - peak_ready_next = 1'b1; - end - else - begin if (~counter_max) begin - counter_next = counter_reg + 4'd1; + counter_next = counter_reg + 5'd1; end - peak_ready_next = 1'b0; - end + if (peak_ready_int) + begin + counter_next = 5'd0; + end + end end default: begin + flag_next = 1'b0; state_next = 2'd0; - counter_next = 4'd0; - peak_ready_next = 1'b0; + counter_next = 5'd0; end endcase end - assign peak_ready = peak_ready_reg; + assign peak_ready = peak_ready_int; + assign peak_debug = peak_ready_reg; endmodule Index: /trunk/MultiChannelUSB/control.v =================================================================== --- /trunk/MultiChannelUSB/control.v (revision 83) +++ /trunk/MultiChannelUSB/control.v (revision 84) @@ -28,4 +28,7 @@ inout wire [17:0] ram_data, + input wire ept_data_ready, + input wire [47:0] ept_data, + output wire i2c_wrreq, output wire [15:0] i2c_data, @@ -36,5 +39,5 @@ reg [23:0] led_counter; - reg [18:0] ram_counter; + reg [19:0] ram_counter; reg [10:0] tst_counter; reg [15:0] int_addr, int_max_addr; @@ -49,4 +52,6 @@ reg int_i2c_wrreq; + reg [47:0] int_ept_data; + reg int_cfg_reset; reg [15:0] int_dst_data, int_dst_addr; @@ -74,5 +79,5 @@ // assign ram_data = int_ram_we ? int_ram_data : 18'bz; // assign ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]}; - assign ram_addr = {1'd0, ram_counter[18:0]}; + assign ram_addr = ram_counter; genvar j; @@ -116,5 +121,5 @@ int_ram_we <= 1'b0; int_ram_data <= 16'd0; - ram_counter <= 19'd0; + ram_counter <= 20'd0; idle_counter <= 5'd0; byte_counter <= 2'd0; @@ -183,5 +188,5 @@ begin tst_counter <= 11'd0; - state <= 5'd6; + state <= 5'd7; end 16'h0004: @@ -189,6 +194,6 @@ int_ram_we <= 1'b1; int_ram_data <= 18'd0; - ram_counter <= 19'd0; - state <= 5'd9; + ram_counter <= 20'd0; + state <= 5'd10; end 16'h0005: @@ -196,5 +201,12 @@ int_i2c_data <= src; int_i2c_wrreq <= 1'b1; - state <= 5'd15; + state <= 5'd16; + end + 16'h0006: + begin + int_ram_we <= 1'b1; + int_ram_data <= 18'd0; + ram_counter <= 20'd0; + state <= 5'd17; end @@ -226,4 +238,9 @@ 5: begin + state <= 5'd6; + end + + 6: + begin if (~tx_full) begin @@ -251,5 +268,5 @@ // tst transfer - 6: + 7: begin crc_reset <= 1'b0; @@ -257,7 +274,7 @@ int_wrreq <= 1'b1; tst_counter <= tst_counter + 11'd1; - state <= 5'd7; - end - 7: + state <= 5'd8; + end + 8: begin if (~tx_full) @@ -266,5 +283,5 @@ if (&tst_counter) begin - state <= 5'd8; + state <= 5'd9; end else @@ -274,5 +291,5 @@ end end - 8: + 9: begin if (~tx_full) @@ -283,40 +300,126 @@ end // ram transfer - 9: + 10: begin crc_reset <= 1'b0; - state <= 5'd10; - end - 10: + state <= 5'd11; + end + 11: begin int_ram_data[8:1] <= ram_counter[7:0]; // int_ram_data[8:1] <= 8'd0; - if (&ram_counter) - begin - state <= 5'd11; + if (&ram_counter[18:0]) + begin + state <= 5'd12; end else begin - state <= 5'd9; - ram_counter <= ram_counter + 19'd1; - end - end - 11: + state <= 5'd10; + ram_counter <= ram_counter + 20'd1; + end + end + 12: begin int_ram_we <= 1'b0; int_ram_data <= 18'd0; - ram_counter <= 19'd0; - state <= 5'd12; - end - 12: + ram_counter <= 20'd0; + state <= 5'd13; + end + 13: begin int_wrreq <= 1'b0; - state <= 5'd13; - end - 13: - begin state <= 5'd14; end 14: + begin + state <= 5'd15; + end + 15: + begin + if (~tx_full) + begin + int_data <= int_ram_q[8:1]; + int_wrreq <= 1'b1; + if (&ram_counter[18:0]) + begin + state <= 5'd0; + end + else + begin + state <= 5'd13; + ram_counter <= ram_counter + 20'd1; + end + end + end + + // i2c write + 16: + begin + crc_reset <= 1'b0; + if (~i2c_full) + begin + int_i2c_wrreq <= 1'b0; + state <= 5'd0; + end + end + + // long sample transfer + 17: + begin + crc_reset <= 1'b0; + if (ept_data_ready) + begin + ram_counter <= ram_counter + 20'd1; + int_ept_data <= ept_data; + state <= 5'd18; + end + end + 18: + begin +// int_ram_data[8:1] <= ram_counter[7:0]; + int_ram_data[8:1] <= int_ept_data[7:0]; + int_ram_data[17:10] <= int_ept_data[15:8]; + ram_counter <= ram_counter + 20'd1; + state <= 5'd19; + end + 19: + begin +// int_ram_data[8:1] <= ram_counter[7:0]; + int_ram_data[8:1] <= int_ept_data[23:16]; + int_ram_data[17:10] <= int_ept_data[31:24]; + ram_counter <= ram_counter + 20'd1; + state <= 5'd20; + end + + 20: + begin +// int_ram_data[8:1] <= ram_counter[7:0]; + int_ram_data[8:1] <= int_ept_data[39:32]; + int_ram_data[17:10] <= int_ept_data[47:40]; + if (&ram_counter) + begin + int_ram_we <= 1'b0; + int_ram_data <= 18'd0; + ram_counter <= 19'd0; + state <= 5'd21; + end + else + begin + state <= 5'd17; + end + end +/* + 21: + begin + int_wrreq <= 1'b0; + state <= 5'd22; + end + + 22: + begin + state <= 5'd23; + end + + 23: begin if (~tx_full) @@ -330,18 +433,51 @@ else begin - state <= 5'd12; - ram_counter <= ram_counter + 19'd1; - end - end - end - - // i2c write - 15: - begin - crc_reset <= 1'b0; - if (~i2c_full) - begin - int_i2c_wrreq <= 1'b0; - state <= 5'd0; + state <= 5'd21; + ram_counter <= ram_counter + 20'd1; + end + end + end +*/ + 21: + begin + int_wrreq <= 1'b0; + state <= 5'd22; + end + + 22: + begin + state <= 5'd23; + end + + 23: + begin + if (~tx_full) + begin + int_data <= int_ram_q[8:1]; + int_wrreq <= 1'b1; + state <= 5'd24; + end + end + + 24: + begin + int_data <= int_ram_q[17:10]; + state <= 5'd25; + end + + 25: + begin + if (~tx_full) + begin + int_wrreq <= 1'b0; + if (&ram_counter) + begin + state <= 5'd0; + end + else + begin + state <= 5'd21; + ram_counter <= ram_counter + 20'd1; + end end end Index: /trunk/MultiChannelUSB/histogram.v =================================================================== --- /trunk/MultiChannelUSB/histogram.v (revision 83) +++ /trunk/MultiChannelUSB/histogram.v (revision 84) @@ -12,5 +12,4 @@ // signal declaration reg [3:0] state_reg, state_next; - reg flag_reg, flag_next; reg wren_reg, wren_next; reg [11:0] addr_reg, addr_next; @@ -18,10 +17,4 @@ wire [W-1:0] q_a_wire, q_b_wire; - - wire [11:0] addr_wire; - wire [W-1:0] data_wire; - - assign addr_wire = (flag_reg) ? data : addr_reg; - assign data_wire = (flag_reg) ? (q_a_wire + 32'd1) : data_reg; altsyncram #( @@ -39,6 +32,6 @@ .outdata_aclr_a("NONE"), .outdata_aclr_b("NONE"), - .outdata_reg_a("UNREGISTERED"), - .outdata_reg_b("UNREGISTERED"), + .outdata_reg_a("CLOCK0"), + .outdata_reg_b("CLOCK0"), .power_up_uninitialized("FALSE"), .read_during_write_mode_mixed_ports("OLD_DATA"), @@ -53,7 +46,7 @@ .clock0(clk), .wren_b(1'b0), - .address_a(addr_wire), + .address_a(addr_reg), .address_b(address), - .data_a(data_wire), + .data_a(data_reg), .data_b(), .q_a(q_a_wire), @@ -79,5 +72,4 @@ if (reset) begin - flag_reg <= 1'b0; wren_reg <= 1'b1; addr_reg <= 12'd0; @@ -87,5 +79,4 @@ else begin - flag_reg <= flag_next; wren_reg <= wren_next; addr_reg <= addr_next; @@ -97,5 +88,4 @@ always @* begin - flag_next = flag_reg; wren_next = wren_reg; addr_next = addr_reg; @@ -106,5 +96,4 @@ begin // nothing to do - flag_next = 1'b0; wren_next = 1'b0; addr_next = 12'd0; @@ -118,5 +107,4 @@ if (&addr_reg) begin - flag_next = 1'b1; wren_next = 1'b0; state_next = 4'd2; @@ -130,16 +118,9 @@ 2: begin + wren_next = 1'b0; if (data_ready) begin - if (&q_a_wire) - begin - flag_next = 1'b0; - state_next = 4'd0; - end - else - begin - wren_next = 1'b1; - state_next = 4'd3; - end + addr_next = data; + state_next = 4'd3; end end @@ -147,11 +128,23 @@ 3: begin - wren_next = 1'b0; - state_next = 4'd2; + state_next = 4'd4; + end + + 4: + begin + if (&q_a_wire) + begin + state_next = 4'd0; + end + else + begin + wren_next = 1'b1; + data_next = q_a_wire + 32'd1; + state_next = 4'd2; + end end default: begin - flag_next = 1'b0; wren_next = 1'b0; addr_next = 12'd0; Index: /trunk/MultiChannelUSB/i2c_fifo.v =================================================================== --- /trunk/MultiChannelUSB/i2c_fifo.v (revision 83) +++ /trunk/MultiChannelUSB/i2c_fifo.v (revision 84) @@ -15,9 +15,9 @@ reg int_rdreq, int_clken, int_sdo, int_scl, int_ack; reg [15:0] int_data; - reg [8:0] counter; + reg [9:0] counter; reg [4:0] state; assign i2c_sda = int_sdo ? 1'bz : 1'b0; - assign i2c_scl = int_scl | (int_clken ? counter[8] : 1'b0); + assign i2c_scl = int_scl | (int_clken ? counter[9] : 1'b0); assign start = int_data[8]; @@ -34,5 +34,5 @@ .overflow_checking("ON"), .underflow_checking("ON"), - .use_eab("OFF")) fifo_tx ( + .use_eab("ON")) fifo_tx ( .rdreq((~int_rdempty) & (int_rdreq) & (&counter)), .aclr(aclr), @@ -50,5 +50,5 @@ always @ (posedge clk) begin - counter <= counter + 9'd1; + counter <= counter + 10'd1; if (&counter) begin Index: /trunk/MultiChannelUSB/oscilloscope.v =================================================================== --- /trunk/MultiChannelUSB/oscilloscope.v (revision 83) +++ /trunk/MultiChannelUSB/oscilloscope.v (revision 84) @@ -11,5 +11,4 @@ // signal declaration reg [3:0] state_reg, state_next; - reg flag_reg, flag_next; reg wren_reg, wren_next; reg [9:0] addr_reg, addr_next; @@ -21,8 +20,4 @@ wire [15:0] q_wire; - - wire [15:0] data_wire; - - assign data_wire = (flag_reg) ? data : data_reg; altsyncram #( @@ -38,5 +33,5 @@ .operation_mode("DUAL_PORT"), .outdata_aclr_b("NONE"), - .outdata_reg_b("UNREGISTERED"), + .outdata_reg_b("CLOCK0"), .power_up_uninitialized("FALSE"), .read_during_write_mode_mixed_ports("OLD_DATA"), @@ -50,5 +45,5 @@ .address_a(addr_reg), .address_b(address), - .data_a(data_wire), + .data_a(data_reg), .q_b(q_wire), .aclr0(1'b0), @@ -76,5 +71,4 @@ begin state_reg <= 4'b1; - flag_reg <= 1'b0; wren_reg <= 1'b1; addr_reg <= 10'd0; @@ -87,5 +81,4 @@ begin state_reg <= state_next; - flag_reg <= flag_next; wren_reg <= wren_next; addr_reg <= addr_next; @@ -100,5 +93,4 @@ begin state_next = state_reg; - flag_next = flag_reg; wren_next = wren_reg; addr_next = addr_reg; @@ -113,5 +105,4 @@ // nothing to do state_next = 4'b0; - flag_next = 1'b0; wren_next = 1'b0; addr_next = 10'd0; @@ -125,5 +116,4 @@ if (&addr_reg) begin - flag_next = 1'b1; wren_next = 1'b0; state_next = 4'd2; @@ -140,4 +130,5 @@ begin wren_next = 1'b1; + data_next = data; state_next = 4'd3; end @@ -152,5 +143,4 @@ if (&counter_reg) begin - flag_next = 1'b0; state_next = 4'd0; end @@ -177,5 +167,4 @@ begin state_next = 4'b0; - flag_next = 1'b0; wren_next = 1'b0; addr_next = 10'd0; Index: /trunk/MultiChannelUSB/suppression.v =================================================================== --- /trunk/MultiChannelUSB/suppression.v (revision 84) +++ /trunk/MultiChannelUSB/suppression.v (revision 84) @@ -0,0 +1,25 @@ +module suppression + ( + input wire clk, + input wire [11:0] data, + input wire [11:0] baseline, + + output wire [11:0] result + ); + + reg [11:0] result_int; + + always @(posedge clk) + begin + if (data > baseline) + begin + result_int <= data - baseline; + end + else + begin + result_int <= 12'd0; + end + end + + assign result = result_int; +endmodule Index: /trunk/MultiChannelUSB/sys_pll.v =================================================================== --- /trunk/MultiChannelUSB/sys_pll.v (revision 84) +++ /trunk/MultiChannelUSB/sys_pll.v (revision 84) @@ -0,0 +1,145 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: sys_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 132 02/25/2009 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sys_pll ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [4:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + + altpll altpll_component ( + .inclk (sub_wire3), + .clk (sub_wire0), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 10, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 17, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + +endmodule Index: /trunk/MultiChannelUSB/test.v =================================================================== --- /trunk/MultiChannelUSB/test.v (revision 83) +++ /trunk/MultiChannelUSB/test.v (revision 84) @@ -2,19 +2,15 @@ ( input wire clk, - output wire tst_clk, - output wire [11:0] tst_data + output wire [11:0] data ); - wire int_clk; reg [11:0] int_data; - reg [2:0] state; - - test_pll test_pll_unit( - .inclk0(clk), - .c0(int_clk)); - - always @(posedge int_clk) + reg [5:0] counter; + reg [5:0] state; + + always @(posedge clk) begin case (state) +/* 0: begin @@ -46,14 +42,348 @@ state <= 3'd0; end +*/ + + 6'd0: + begin + int_data <= 12'h030; + state <= 6'd1; + end + + 6'd1: + begin + int_data <= 12'h034; + state <= 6'd2; + end + + 6'd2: + begin + int_data <= 12'h081; + state <= 6'd3; + end + + 6'd3: + begin + int_data <= 12'h0f5; + state <= 6'd4; + end + + 6'd4: + begin + int_data <= 12'h10a; + state <= 6'd5; + end + + 6'd5: + begin + int_data <= 12'h11a; + state <= 6'd6; + end + + 6'd6: + begin + int_data <= 12'h124; + state <= 6'd7; + end + + 6'd7: + begin + int_data <= 12'h124; + state <= 6'd8; + end + + 6'd8: + begin + int_data <= 12'h12b; + state <= 6'd9; + end + + 6'd9: + begin + int_data <= 12'h12a; + state <= 6'd10; + end + + 6'd10: + begin + int_data <= 12'h12a; + state <= 6'd11; + end + + 6'd11: + begin + int_data <= 12'h12b; + state <= 6'd12; + end + + 6'd12: + begin + int_data <= 12'h12a; + state <= 6'd13; + end + + 6'd13: + begin + int_data <= 12'h12e; + state <= 6'd14; + end + + 6'd14: + begin + int_data <= 12'h12b; + state <= 6'd15; + end + + 6'd15: + begin + int_data <= 12'h12b; + state <= 6'd16; + end + + 6'd16: + begin + int_data <= 12'h12e; + state <= 6'd17; + end + + 6'd17: + begin + int_data <= 12'h12b; + state <= 6'd18; + end + + 6'd18: + begin + int_data <= 12'h12a; + state <= 6'd19; + end + + 6'd19: + begin + int_data <= 12'h12e; + state <= 6'd20; + end + + 6'd20: + begin + int_data <= 12'h12b; + state <= 6'd21; + end + + 6'd21: + begin + int_data <= 12'h12e; + state <= 6'd22; + end + + 6'd22: + begin + int_data <= 12'h12f; + state <= 6'd23; + end + + 6'd23: + begin + int_data <= 12'h12f; + state <= 6'd24; + end + + 6'd24: + begin + int_data <= 12'h12b; + state <= 6'd25; + end + + 6'd25: + begin + int_data <= 12'h12b; + state <= 6'd26; + end + + 6'd26: + begin + int_data <= 12'h12b; + state <= 6'd27; + end + + 6'd27: + begin + int_data <= 12'h12e; + state <= 6'd28; + end + + 6'd28: + begin + int_data <= 12'h12e; + state <= 6'd29; + end + + 6'd29: + begin + int_data <= 12'h12e; + state <= 6'd30; + end + + 6'd30: + begin + int_data <= 12'h12e; + state <= 6'd31; + end + + 6'd31: + begin + int_data <= 12'h12b; + state <= 6'd32; + end + + 6'd32: + begin + int_data <= 12'h12b; + state <= 6'd33; + end + + 6'd33: + begin + int_data <= 12'h12b; + state <= 6'd34; + end + + 6'd34: + begin + int_data <= 12'h12e; + state <= 6'd35; + end + + 6'd35: + begin + int_data <= 12'h12e; + state <= 6'd36; + end + + 6'd36: + begin + int_data <= 12'h12e; + state <= 6'd37; + end + + 6'd37: + begin + int_data <= 12'h12e; + state <= 6'd38; + end + + 6'd38: + begin + int_data <= 12'h12f; + state <= 6'd39; + end + + 6'd39: + begin + int_data <= 12'h12b; + state <= 6'd40; + end + + 6'd40: + begin + int_data <= 12'h12e; + state <= 6'd41; + end + + 6'd41: + begin + int_data <= 12'h12f; + state <= 6'd42; + end + + 6'd42: + begin + int_data <= 12'h0fb; + state <= 6'd43; + end + + 6'd43: + begin + int_data <= 12'h07e; + state <= 6'd44; + end + + 6'd44: + begin + int_data <= 12'h070; + state <= 6'd45; + end + + 6'd45: + begin + int_data <= 12'h05a; + state <= 6'd46; + end + + 6'd46: + begin + int_data <= 12'h045; + state <= 6'd47; + end + + 6'd47: + begin + int_data <= 12'h03f; + state <= 6'd48; + end + + 6'd48: + begin + int_data <= 12'h03b; + state <= 6'd49; + end + + 6'd49: + begin + int_data <= 12'h034; + state <= 6'd50; + end + + 6'd50: + begin + int_data <= 12'h035; + state <= 6'd51; + end + + 6'd51: + begin + int_data <= 12'h034; + state <= 6'd52; + end + + 6'd52: + begin + int_data <= 12'h034; + state <= 6'd53; + end + + 6'd53: + begin + int_data <= 12'h030; + state <= 6'd54; + end + + 6'd54: + begin + int_data <= 12'h030; + counter <= counter + 6'd1; + if (&counter) + begin + state <= 6'd0; + end + end default: begin - state <= 3'd0; + state <= 6'd0; end endcase end - assign tst_clk = int_clk; - assign tst_data = int_data; + assign data = int_data; endmodule Index: /trunk/MultiChannelUSB/usb_fifo.v =================================================================== --- /trunk/MultiChannelUSB/usb_fifo.v (revision 83) +++ /trunk/MultiChannelUSB/usb_fifo.v (revision 84) @@ -35,5 +35,5 @@ .overflow_checking("ON"), .underflow_checking("ON"), - .use_eab("OFF"), + .use_eab("ON"), .write_aclr_synch("OFF")) fifo_tx ( .aclr(aclr), @@ -62,5 +62,5 @@ .overflow_checking("ON"), .underflow_checking("ON"), - .use_eab("OFF"), + .use_eab("ON"), .write_aclr_synch("OFF")) fifo_rx ( .aclr(aclr), Index: /trunk/MultiChannelUSB/uwt_bior31.v =================================================================== --- /trunk/MultiChannelUSB/uwt_bior31.v (revision 83) +++ /trunk/MultiChannelUSB/uwt_bior31.v (revision 84) @@ -16,5 +16,5 @@ localparam index2 = 2 << (L - 1); localparam index3 = 3 << (L - 1); - localparam peak_index = ((3 << (L - 1)) + 1) >> 1; + localparam peak_index = ((index3 + 1) >> 1) + 1; localparam peak_shift = ((L - 1) << 1) + (L - 1); localparam zero = 32'h80000000; @@ -26,4 +26,10 @@ reg [31:0] a_reg, a_next; reg [31:0] peak_reg, peak_next; + + reg [31:0] tmp1_reg, tmp1_next; + reg [31:0] tmp2_reg, tmp2_next; + + reg less_reg, less_next; + reg more_reg, more_next; reg [1:0] flag_reg; @@ -39,4 +45,8 @@ peak_reg <= 0; flag_reg <= 0; + tmp1_reg <= 0; + tmp2_reg <= 0; + less_reg <= 1'b0; + more_reg <= 1'b0; for(i = 0; i <= index3; i = i + 1) @@ -51,7 +61,12 @@ peak_reg <= peak_next; - flag_reg[0] <= (d_reg > zero) & (d_next <= zero); - flag_reg[1] <= (d_reg < zero) & (d_next >= zero); - + tmp1_reg <= tmp1_next; + tmp2_reg <= tmp2_next; + less_reg <= less_next; + more_reg <= more_next; + + flag_reg[0] <= (more_reg) & (~more_next); + flag_reg[1] <= (less_reg) & (~less_next); + // Tapped delay line: shift one for(i = 0; i < index3; i = i + 1) @@ -70,4 +85,14 @@ // The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1] + tmp1_next = tap[index3] + {tap[index2][30:0], 1'b0} + tap[index2]; + tmp2_next = {tap[index1][30:0], 1'b0} + tap[index1] + tap[0]; + + d_next = zero - tmp1_reg + tmp2_reg; + a_next = tmp1_reg + tmp2_reg; + + more_next = (d_reg > zero); + less_next = (d_reg < zero); + +/* d_next = zero - (tap[index3]) - (tap[index2] << 1) - tap[index2] @@ -76,8 +101,8 @@ a_next = (tap[index3]) - + (tap[index2] << 1) + tap[index2] + + {tap[index2] << 1} + tap[index2] + (tap[index1] << 1) + tap[index1] + (tap[0]); - +*/ peak_next = (tap[peak_index] >> peak_shift); end