Index: trunk/MultiChannelUSB/Paella.qsf
===================================================================
--- trunk/MultiChannelUSB/Paella.qsf	(revision 71)
+++ trunk/MultiChannelUSB/Paella.qsf	(revision 72)
@@ -56,5 +56,7 @@
 set_global_assignment -name VERILOG_FILE control.v
 set_global_assignment -name VERILOG_FILE analyser.v
+set_global_assignment -name VERILOG_FILE baseline.v
 set_global_assignment -name VERILOG_FILE histogram.v
+set_global_assignment -name VERILOG_FILE trigger.v
 set_global_assignment -name VERILOG_FILE oscilloscope.v
 set_global_assignment -name VERILOG_FILE usb_fifo.v
Index: trunk/MultiChannelUSB/Paella.v
===================================================================
--- trunk/MultiChannelUSB/Paella.v	(revision 71)
+++ trunk/MultiChannelUSB/Paella.v	(revision 72)
@@ -6,5 +6,5 @@
 		inout	wire	[3:0]	TRG,
 		inout	wire			I2C_SDA,
-		output	wire			I2C_SCL,
+		inout	wire			I2C_SCL,
 		inout	wire	[4:0]	CON_A,
 		inout	wire	[15:0]	CON_B,
@@ -43,4 +43,6 @@
 	);
 
+	localparam	N		=	3;
+
 	//	Turn output ports off
 /*
@@ -105,16 +107,38 @@
 	);
 	
-	reg 			ana_reset [3:0];
-	wire			ana_peak_ready [3:0];
-	wire	[11:0]	ana_peak [3:0];
-
-	reg 			osc_reset [3:0];
-	reg 	[9:0]	osc_addr [3:0];
-	wire	[9:0]	osc_start_addr [3:0];
-	wire	[15:0]	osc_q [3:0];
-
-	reg 			hst_reset [3:0];
-	reg 	[11:0]	hst_addr [3:0];
-	wire	[31:0]	hst_q [3:0];
+	reg 			bln_reset [N-1:0];
+	wire	[11:0]	baseline [N-1:0];
+	wire	[11:0]	bln_baseline [N-1:0];
+
+	reg 			ana_reset [N-1:0];
+	wire			ana_peak_ready [N-1:0];
+	wire	[11:0]	ana_peak [N-1:0];
+
+	reg				osc_reset [N-1:0];
+	reg 	[9:0]	osc_addr [N-1:0];
+	wire	[9:0]	osc_start_addr [N-1:0];
+	wire	[15:0]	osc_q [N-1:0];
+	wire			osc_trig [N-1:0];
+
+	wire	[3:0]	osc_mux_sel [N-1:0];
+	wire	[11:0]	osc_mux_data [N-1:0];
+
+	wire 			trg_reset [N-1:0];
+	wire	[3:0]	trg_mux_sel [N-1:0];
+	wire	[11:0]	trg_mux_data [N-1:0];
+	wire	[11:0]	trg_thrs [N-1:0];
+
+	reg 			hst_reset [N-1:0];
+	reg 	[11:0]	hst_addr [N-1:0];
+	wire			hst_data_ready [N-1:0];
+	wire	[11:0]	hst_data [N-1:0];
+	wire	[31:0]	hst_q [N-1:0];
+
+
+	wire	[3:0]	hst_mux_sel [N-1:0];
+	wire	[12:0]	hst_mux_data [N-1:0];
+
+	wire	[3:0]	bln_mux_sel [N-1:0];
+	wire	[11:0]	bln_mux_data [N-1:0];
 
 	wire 			mux_reset, mux_type;
@@ -126,30 +150,37 @@
 	reg 	[15:0]	mux_min_addr, mux_max_addr;
 
-	wire			adc_clk [3:0];
-	wire			adc_data_ready [3:0];
-	wire 	[11:0]	adc_data [3:0];
-
-    wire	[11:0]	raw_data [3:0];
-    wire	[11:0]	uwt_data [3:0];
-    wire	[1:0]	uwt_flag [3:0];
+	wire			adc_clk [N-1:0];
+	wire 	[11:0]	adc_data [N-1:0];
+
+	wire			data_ready [N-1:0];
+    wire	[11:0]	data [N-1:0];
+    wire	[11:0]	int_data [N-1:0];
     
-    wire	[16:0]	osc_thrs [3:0];
-    wire			adc_pola [3:0];
-
+/*
     assign	osc_thrs[0] = 16'd40;
     assign	osc_thrs[1] = 16'd60;
     assign	osc_thrs[2] = 16'd40;
     assign	osc_thrs[3] = 16'd1650;
-
-    assign	adc_pola[0] = 1'b1;
-    assign	adc_pola[1] = 1'b1;
-    assign	adc_pola[2] = 1'b1;
-    assign	adc_pola[3] = 1'b0;
+*/
+	wire 	[31:0]	uwt_d1 [N-1:0];
+	wire 	[31:0]	uwt_a1 [N-1:0];
+	wire 	[31:0]	uwt_peak1 [N-1:0];
+	wire 	[31:0]	uwt_d2 [N-1:0];
+	wire 	[31:0]	uwt_a2 [N-1:0];
+	wire 	[31:0]	uwt_peak2 [N-1:0];
+	wire 	[31:0]	uwt_d3 [N-1:0];
+	wire 	[31:0]	uwt_a3 [N-1:0];
+	wire 	[31:0]	uwt_peak3 [N-1:0];
+
+	wire 	[1:0]	uwt_flag1 [N-1:0];
+	wire 	[1:0]	uwt_flag2 [N-1:0];
+	wire 	[1:0]	uwt_flag3 [N-1:0];
 
     assign	adc_clk[0] = ADC_FCO;
     assign	adc_clk[1] = ADC_FCO;
 //    assign	adc_clk[2] = ADC_FCO;
-
+/*
     assign	adc_clk[3] = ADC_FCO;
+*/
 /*    
     assign	adc_clk[3] = CON_CCLK[0];
@@ -196,63 +227,182 @@
 		.sdoin());
 */
-/*
+
 	adc_lvds #(
-		.size(3),
+		.size(2),
 		.width(12)) adc_lvds_unit (
 		.lvds_dco(ADC_DCO),
 //		.lvds_dco(adc_pll_clk),
 		.lvds_fco(ADC_FCO),
-		.lvds_d(ADC_D),
-		.adc_data({ adc_data[0],
-					adc_data[1],
-					adc_data[2] }));
-*/ 
+		.lvds_d(ADC_D[1:0]),
+		.adc_data({	adc_data[1],
+					adc_data[0] }));
+
+
+	reg		[15:0]	cfg_memory [31:0];
+	wire	[15:0]	cfg_src_data;
+	wire	[15:0]	cfg_src_addr, cfg_dst_data, cfg_dst_addr;
+
+	wire			cfg_polarity [N-1:0];
+	wire	[11:0]	cfg_baseline [N-1:0];
+	wire	[11:0]	cfg_hst_threshold [N-1:0];
+	wire	[11:0]	cfg_trg_threshold [N-1:0];
+
+	wire 			cfg_reset;
+
+	integer j;
+
+	always @(posedge CLK_50MHz)
+	begin
+		if (cfg_reset)
+		begin
+			for(j = 0; j <= 31; j = j + 1)
+			begin
+				cfg_memory[j] <= 16'd0;
+			end
+		end
+		else
+		begin
+			cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
+		end
+	end
+
 	genvar i;
+
 	generate
-		for (i = 0; i < 3; i = i + 1)
+		for (i = 0; i < N; i = i + 1)
 		begin : MCA_CHAIN
+
+			assign cfg_polarity[i] = cfg_memory[10][4*i];
+			assign cfg_baseline[i] = cfg_memory[11+i][11:0];
+			assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
+			assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
+
+			assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
+			assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
+			assign hst_mux_sel[i] = cfg_memory[20+i][11:8];
+			assign bln_mux_sel[i] = cfg_memory[20+i][15:12];
+
 			adc_fifo adc_fifo_unit (
 				.adc_clk(adc_clk[i]),
 				.adc_data(adc_data[i]),
-				.polarity(adc_pola[i]),
-				.clk(CLK_50MHz),
-				.ready(adc_data_ready[i]),
-				.raw_data(raw_data[i]),
-				.uwt_data({uwt_flag[i], uwt_data[i]}));
+				.clk(CLK_50MHz),
+				.data_ready(data_ready[i]),
+				.data(int_data[i]));
+
+			assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
+
+			uwt_bior31 #(.L(1)) uwt_1_unit (
+				.clk(CLK_50MHz),
+				.data_ready(data_ready[i]),
+				.x({20'h00000, data[i]}),
+				.d(uwt_d1[i]),
+				.a(uwt_a1[i]),
+				.peak(uwt_peak1[i]),
+				.flag(uwt_flag1[i]));
+		
+			uwt_bior31 #(.L(2)) uwt_2_unit (
+				.clk(CLK_50MHz),
+				.data_ready(data_ready[i]),
+				.x(uwt_a1[i]),
+				.d(uwt_d2[i]),
+				.a(uwt_a2[i]),
+				.peak(uwt_peak2[i]),
+				.flag(uwt_flag2[i]));
+		
+			uwt_bior31 #(.L(3)) uwt_3_unit (
+				.clk(CLK_50MHz),
+				.data_ready(data_ready[i]),
+				.x(uwt_a2[i]),
+				.d(uwt_d3[i]),
+				.a(uwt_a3[i]),
+				.peak(uwt_peak3[i]),
+				.flag(uwt_flag3[i]));
+
+			lpm_mux #(
+				.lpm_size(4),
+				.lpm_type("LPM_MUX"),
+				.lpm_width(12),
+				.lpm_widths(2)) osc_mux_unit (
+				.sel(osc_mux_sel[i][1:0]),
+				.data({	uwt_a3[i][20:9],
+						uwt_a2[i][17:6],
+						uwt_a1[i][14:3],
+						data[i] }),
+				.result(osc_mux_data[i]));
+
+			lpm_mux #(
+				.lpm_size(4),
+				.lpm_type("LPM_MUX"),
+				.lpm_width(12),
+				.lpm_widths(2)) trg_mux_unit (
+				.sel(trg_mux_sel[i][1:0]),
+				.data({	uwt_a3[i][20:9],
+						uwt_a2[i][17:6],
+						uwt_a1[i][14:3],
+						data[i] }),
+				.result(trg_mux_data[i]));
+
+			lpm_mux #(
+				.lpm_size(2),
+				.lpm_type("LPM_MUX"),
+				.lpm_width(13),
+				.lpm_widths(1)) hst_mux_unit (
+				.sel(hst_mux_sel[i][0]),
+				.data({	{ana_peak[i], ana_peak_ready[i]},
+						{data[i], data_ready[i]} }),
+				.result(hst_mux_data[i]));
 	
+			lpm_mux #(
+				.lpm_size(2),
+				.lpm_type("LPM_MUX"),
+				.lpm_width(12),
+				.lpm_widths(1)) bln_mux_unit (
+				.sel(bln_mux_sel[i][0]),
+				.data({bln_baseline[i], cfg_baseline[i]}),
+				.result(bln_mux_data[i]));
+
+			baseline baseline_unit (
+				.clk(CLK_50MHz),
+				.reset(bln_reset[i]),
+				.data_ready(data_ready[i]),
+				.uwt_flag(uwt_flag3[i]),
+				.uwt_data(uwt_peak3[i]),
+				.baseline(bln_baseline[i]));
+
 			analyser analyser_unit (
 				.clk(CLK_50MHz),
 				.reset(ana_reset[i]),
-				.data_ready(adc_data_ready[i]),
-				.uwt_flag(uwt_flag[i]),
-				.uwt_data(uwt_data[i]),
-				.threshold(12'd10),
+				.data_ready(data_ready[i]),
+				.uwt_flag(uwt_flag3[i]),
+				.uwt_data(uwt_peak3[i]),
 				.peak_ready(ana_peak_ready[i]),
 				.peak(ana_peak[i]));
 
-			histogram histogram_unit (
+			assign hst_data[i] = (hst_mux_data[i][12:1] > bln_mux_data[i]) ? (hst_mux_data[i][12:1] - bln_mux_data[i]) : 12'd0;
+			assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
+
+			histogram #(.W(32)) histogram_unit (
 				.clk(CLK_50MHz),
 				.reset(hst_reset[i]),
-				.data_ready(adc_data_ready[i]),
-				.data(raw_data[i]),
-//				.data(uwt_data[i]),
+				.data_ready(hst_data_ready[i]),
+				.data(hst_data[i]),
 				.address(hst_addr[i]),
 				.q(hst_q[i]));
-/*
-			histogram histogram_unit (
-				.clk(CLK_50MHz),
-				.reset(hst_reset[i]),
-				.data_ready(ana_peak_ready[i]),
-				.data(ana_peak[i]),
-				.address(hst_addr[i]),
-				.q(hst_q[i]));
-*/			
+
+			trigger trigger_unit (
+				.clk(CLK_50MHz),
+				.reset(trg_reset[i]),
+				.data_ready(data_ready[i]),
+				.data(trg_mux_data[i]),
+				.threshold(cfg_trg_threshold[i]),
+				.trigger(osc_trig[i]));
+
+			
 			oscilloscope oscilloscope_unit (
 				.clk(CLK_50MHz),
 				.reset(osc_reset[i]),
-				.data_ready(adc_data_ready[i]),
-				.raw_data(raw_data[i]),
-				.uwt_data(uwt_data[i]),
-				.threshold(osc_thrs[i]),
+				.data_ready(data_ready[i]),
+				.data(osc_mux_data[i]),
+				.trigger(osc_trig[i]),
 				.address(osc_addr[i]),
 				.start_address(osc_start_addr[i]),
@@ -261,9 +411,7 @@
 	endgenerate
 
-	integer j;
-
 	always @*
 	begin
-		for (j = 0; j < 4; j = j + 1)
+		for (j = 0; j < N; j = j + 1)
 		begin
 			osc_reset[j] = 1'b0;
@@ -273,6 +421,8 @@
 		end
 
-		case({mux_type, mux_chan})
-			3'b000, 3'b001, 3'b010, 3'b011:
+		case(mux_type)
+//		case({mux_type, mux_chan})
+			1'b0:
+//			3'b000, 3'b001, 3'b010, 3'b011:
 			begin
 				osc_reset[mux_chan] = mux_reset;
@@ -283,5 +433,6 @@
 			end
 
-			3'b100, 3'b101, 3'b110, 3'b111:
+			1'b1:
+//			3'b100, 3'b101, 3'b110, 3'b011:
 			begin
 				hst_reset[mux_chan] = mux_reset;
@@ -332,4 +483,9 @@
 	control control_unit (
 		.clk(CLK_50MHz),
+		.cfg_reset(cfg_reset),
+		.cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
+		.cfg_src_addr(cfg_src_addr),
+		.cfg_dst_data(cfg_dst_data),
+		.cfg_dst_addr(cfg_dst_addr),
 		.rx_empty(usb_rx_empty),
 		.tx_full(usb_tx_full),
Index: trunk/MultiChannelUSB/adc_fifo.v
===================================================================
--- trunk/MultiChannelUSB/adc_fifo.v	(revision 71)
+++ trunk/MultiChannelUSB/adc_fifo.v	(revision 72)
@@ -3,56 +3,15 @@
 		input	wire			adc_clk,
 		input	wire	[11:0]	adc_data,
-		input	wire			polarity,
 
 		input	wire			clk,
-
-		output	wire			ready,
-		output	wire	[11:0]	raw_data,
-		output	wire	[13:0]	uwt_data
+		output	wire			data_ready,
+		output	wire	[11:0]	data
 	);
 
-	wire 	[31:0]	uwt_d1, uwt_a1, uwt_peak1;
-	wire 	[31:0]	uwt_d2, uwt_a2, uwt_peak2;
-	wire 	[31:0]	uwt_d3, uwt_a3, uwt_peak3;
-	wire 	[1:0]	uwt_flag1, uwt_flag2, uwt_flag3;
-
-	wire	[11:0]	int_raw_q;
-	wire	[13:0]	int_uwt_q;
-
-	reg		[11:0]	int_raw_data;
-	reg		[13:0]	int_uwt_data;
-
-	wire	[1:0]	wrfull;
+	wire	[11:0]	int_q;
+	reg		[11:0]	int_data;
 	
-	reg				state;
-	reg				int_rdreq, int_ready;
-	wire			int_rdempty;
-
-	wire	[11:0]	int_adc_data;
-	assign	int_adc_data = (polarity) ? (12'hfff - adc_data) : (adc_data);
-
-	uwt_bior31 #(.L(1)) uwt_1_unit (
-		.clk(adc_clk),
-		.x({20'h00000, int_adc_data}),
-		.d(uwt_d1),
-		.a(uwt_a1),
-		.peak(uwt_peak1),
-		.flag(uwt_flag1));
-
-	uwt_bior31 #(.L(2)) uwt_2_unit (
-		.clk(adc_clk),
-		.x(uwt_a1),
-		.d(uwt_d2),
-		.a(uwt_a2),
-		.peak(uwt_peak2),
-		.flag(uwt_flag2));
-
-	uwt_bior31 #(.L(3)) uwt_3_unit (
-		.clk(adc_clk),
-		.x(uwt_a2),
-		.d(uwt_d3),
-		.a(uwt_a3),
-		.peak(uwt_peak3),
-		.flag(uwt_flag3));
+	reg				state, int_rdreq, int_data_ready;
+	wire			int_wrfull, int_rdempty;
 
 	dcfifo #(
@@ -67,42 +26,15 @@
 		.overflow_checking("ON"),
 		.underflow_checking("ON"),
-		.use_eab("ON"),
-		.write_aclr_synch("OFF")) fifo_raw (
+		.use_eab("OFF"),
+		.write_aclr_synch("OFF")) fifo_unit (
 		.aclr(1'b0),
-		.data(int_adc_data),
+		.data(adc_data),
 		.rdclk(clk),
 		.rdreq((~int_rdempty) & int_rdreq),
 		.wrclk(adc_clk),
-		.wrreq(~wrfull[0]),
-		.q(int_raw_q),
+		.wrreq(~int_wrfull),
+		.q(int_q),
 		.rdempty(int_rdempty),
-		.wrfull(wrfull[0]),
-		.rdfull(),
-		.rdusedw(),
-		.wrempty(),
-		.wrusedw());
-
-	dcfifo #(
-		.intended_device_family("Cyclone III"),
-		.lpm_numwords(16),
-		.lpm_showahead("ON"),
-		.lpm_type("dcfifo"),
-		.lpm_width(14),
-		.lpm_widthu(4),
-		.rdsync_delaypipe(4),
-		.wrsync_delaypipe(4),
-		.overflow_checking("ON"),
-		.underflow_checking("ON"),
-		.use_eab("ON"),
-		.write_aclr_synch("OFF")) fifo_uwt (
-		.aclr(1'b0),
-		.data({uwt_flag3, uwt_peak3[11:0]}),
-		.rdclk(clk),
-		.rdreq((~int_rdempty) & int_rdreq),
-		.wrclk(adc_clk),
-		.wrreq(~wrfull[1]),
-		.q(int_uwt_q),
-		.rdempty(),
-		.wrfull(wrfull[1]),
+		.wrfull(int_wrfull),
 		.rdfull(),
 		.rdusedw(),
@@ -116,5 +48,5 @@
 			begin
 				int_rdreq <= 1'b1;
-				int_ready <= 1'b0;
+				int_data_ready <= 1'b0;
 				state <= 1'b1;
 			end
@@ -124,8 +56,7 @@
 				if (~int_rdempty)
 				begin
-					int_raw_data <= int_raw_q;
-					int_uwt_data <= int_uwt_q;
+					int_data <= int_q;
 					int_rdreq <= 1'b0;
-					int_ready <= 1'b1;
+					int_data_ready <= 1'b1;
 					state <= 1'b0;
 				end
@@ -135,5 +66,5 @@
 			begin
 				int_rdreq <= 1'b1;
-				int_ready <= 1'b0;
+				int_data_ready <= 1'b0;
 				state <= 1'b1;
 			end
@@ -141,7 +72,6 @@
 	end
 	
-	assign	ready = int_ready;
-	assign	raw_data = int_raw_data;
-	assign	uwt_data = int_uwt_data;
+	assign	data_ready = int_data_ready;
+	assign	data = int_data;
 
 endmodule
Index: trunk/MultiChannelUSB/adc_lvds.v
===================================================================
--- trunk/MultiChannelUSB/adc_lvds.v	(revision 71)
+++ trunk/MultiChannelUSB/adc_lvds.v	(revision 72)
@@ -7,5 +7,5 @@
 		input	wire						lvds_dco,
 		input	wire						lvds_fco,
- 		input	wire	[2:0]				lvds_d,
+ 		input	wire	[size-1:0]			lvds_d,
 
 		output	wire	[size*width-1:0]	adc_data
@@ -61,5 +61,5 @@
 
 	generate
-		for (j = 1; j < size; j = j + 1)
+		for (j = 0; j < size; j = j + 1)
 		begin : ADC_LVDS_OUTPUT
 			assign adc_data[j*width+width-1:j*width] = int_adc_data[j];
Index: trunk/MultiChannelUSB/analyser.v
===================================================================
--- trunk/MultiChannelUSB/analyser.v	(revision 71)
+++ trunk/MultiChannelUSB/analyser.v	(revision 72)
@@ -5,5 +5,4 @@
 		input	wire	[1:0]	uwt_flag,
 		input	wire	[11:0]	uwt_data,
-		input	wire	[11:0]	threshold,
 		output	wire			peak_ready,
 		output	wire	[11:0]	peak
@@ -14,13 +13,5 @@
 	reg				peak_ready_reg, peak_ready_next;
 	reg		[11:0]	peak_reg, peak_next;
-	reg		[15:0]	buffer [15:0];
-	wire	[15:0]	sample;
-	wire	[11:0]	baseline;
 
-	integer			i;
-
-	assign	sample = {4'd0, uwt_data};
-	assign	baseline = buffer[15][15:4];
-	
 	always @(posedge clk)
 	begin
@@ -31,9 +22,4 @@
 			peak_ready_reg <= 1'b0;
 			peak_reg <= 12'd0;
-
-			for(i = 0; i <= 15; i = i + 1)
-			begin
-				buffer[i] <= 12'd0;
-			end
 		end
 		else
@@ -42,14 +28,5 @@
 			counter_reg <= counter_next;
 			peak_ready_reg <= peak_ready_next;
-			peak_reg <= peak_next;
-			
-			if (data_ready & uwt_flag[1])
-			begin
-				for(i = 0; i < 15; i = i + 1)
-				begin
-					buffer[i+1] <= buffer[i] + sample;
-				end
-				buffer[0] <= sample;
-			end
+			peak_reg <= peak_next;			
 		end
 	end
@@ -92,6 +69,6 @@
 				if (data_ready & uwt_flag[0])
 				begin
-					peak_next = (uwt_data > baseline) ? (uwt_data - baseline) : 12'd0;
-					peak_ready_next = (peak_next > threshold);
+					peak_next = uwt_data;
+					peak_ready_next = 1'b1;
                 end
                 else
Index: trunk/MultiChannelUSB/control.v
===================================================================
--- trunk/MultiChannelUSB/control.v	(revision 71)
+++ trunk/MultiChannelUSB/control.v	(revision 72)
@@ -2,4 +2,9 @@
 	(
 		input	wire			clk,
+
+		output	wire			cfg_reset,
+		input	wire	[15:0]	cfg_src_data,
+		output	wire	[15:0]	cfg_src_addr, cfg_dst_data, cfg_dst_addr,
+
 		input	wire			rx_empty, tx_full,
 		input	wire	[7:0]	rx_data,
@@ -44,4 +49,6 @@
 	reg 			int_i2c_wrreq;
 
+	reg 			int_cfg_reset;
+	reg		[15:0]	int_dst_data, int_dst_addr;
 
 	wire			crc_error = 1'b0;
@@ -54,8 +61,7 @@
 	wire	[15:0]	src, dst;
 
-	reg		[15:0]	memory [15:0];
 	reg		[7:0]	buffer [7:0];
 
-	assign	src = (buffer[0][7]) ? memory[buffer[3][3:0]] : {buffer[2], buffer[3]};
+	assign	src = (buffer[0][7]) ? cfg_src_data : {buffer[2], buffer[3]};
 	assign	dst = {1'b0, buffer[0][6:0], buffer[1]};
 
@@ -113,4 +119,5 @@
 				idle_counter <= 5'd0;
 				byte_counter <= 3'd0;
+				int_cfg_reset <= 1'b0;
 				state <= 5'd1;
 			end
@@ -147,9 +154,12 @@
 				if (~crc_error)
 				begin
-					memory[dst[3:0]] <= src;
+					int_dst_addr <= dst;
+					int_dst_data <= src;
+//					memory[dst[3:0]] <= src;
 				
 					case (dst)
 						16'h0000:
 						begin
+							int_cfg_reset <= 1'b1;
 							state <= 5'd0;
 						end
@@ -187,4 +197,9 @@
 							int_i2c_wrreq <= 1'b1;
 							state <= 5'd15;
+						end
+
+						default:
+						begin
+							state <= 5'd0;
 						end
 					endcase
@@ -339,4 +354,8 @@
 	end
 	
+	assign	cfg_reset = int_cfg_reset;
+	assign	cfg_src_addr = {buffer[2], buffer[3]};
+	assign	cfg_dst_data = int_dst_data;
+	assign	cfg_dst_addr = int_dst_addr;
 	assign	mux_reset = int_reset;
 	assign	mux_type = int_type;
Index: trunk/MultiChannelUSB/histogram.v
===================================================================
--- trunk/MultiChannelUSB/histogram.v	(revision 71)
+++ trunk/MultiChannelUSB/histogram.v	(revision 72)
@@ -1,8 +1,11 @@
 module histogram
+	#(
+		parameter	W	=	32 // bin resolution
+	)
 	(
 		input	wire			clk, reset,
 		input	wire			data_ready,
 		input	wire	[11:0]  data, address,
-		output	wire	[31:0]  q
+		output	wire	[W-1:0]  q
 	);
 	
@@ -12,10 +15,10 @@
 	reg				wren_reg, wren_next;
 	reg		[11:0]	addr_reg, addr_next;
-	reg		[31:0]	data_reg, data_next;
+	reg		[W-1:0]	data_reg, data_next;
 
-	wire	[31:0]	q_a_wire, q_b_wire;
+	wire	[W-1:0]	q_a_wire, q_b_wire;
 	
 	wire	[11:0]	addr_wire;
-	wire	[31:0]	data_wire;
+	wire	[W-1:0]	data_wire;
 	
 	assign	addr_wire = (flag_reg) ? data : addr_reg;
@@ -42,6 +45,6 @@
 		.widthad_a(12),
 		.widthad_b(12),
-		.width_a(32),
-		.width_b(32),
+		.width_a(W),
+		.width_b(W),
 		.width_byteena_a(1),
 		.width_byteena_b(1),
Index: trunk/MultiChannelUSB/oscilloscope.v
===================================================================
--- trunk/MultiChannelUSB/oscilloscope.v	(revision 71)
+++ trunk/MultiChannelUSB/oscilloscope.v	(revision 72)
@@ -2,6 +2,6 @@
 	(
 		input	wire			clk, reset,
-		input	wire			data_ready,
-		input	wire	[15:0]  raw_data, uwt_data, threshold,
+		input	wire			data_ready, trigger,
+		input	wire	[15:0]  data,
 		input	wire	[9:0]	address,
 		output	wire	[9:0]	start_address,
@@ -24,5 +24,5 @@
 	wire	[15:0]	data_wire;
 	
-	assign	data_wire = (flag_reg) ? raw_data : data_reg;
+	assign	data_wire = (flag_reg) ? data : data_reg;
 
 	altsyncram #(
@@ -159,7 +159,6 @@
 					state_next = 4'd2;
 
-					if ((~trig_reg)
-						& (counter_reg == 10'd512)
-						& (uwt_data >= threshold))
+					if ((~trig_reg) & (trigger) 
+						& (counter_reg == 10'd512))
 					begin
 						// trigger
Index: trunk/MultiChannelUSB/uwt_bior31.v
===================================================================
--- trunk/MultiChannelUSB/uwt_bior31.v	(revision 71)
+++ trunk/MultiChannelUSB/uwt_bior31.v	(revision 72)
@@ -5,4 +5,5 @@
 	(
 		input	wire			clk, reset,
+		input	wire			data_ready,
 		input	wire	[31:0]	x,
 		output	wire	[31:0]	d,
@@ -30,5 +31,5 @@
 	integer			i;
 	
-	always @(posedge clk, posedge reset)
+	always @(posedge clk)
 	begin
 		if (reset)
@@ -44,5 +45,5 @@
 			end
 		end
-		else
+		else if (data_ready)
 		begin
 			d_reg <= d_next;